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1. 发明授权

US5861649A Trench-type semiconductor memory device 失效
标题翻译：沟槽型半导体存储器件
公开(公告)号：US5861649A
公开(公告)日：1999-01-19
申请号：US871530
申请日：1992-04-21
申请人： Hiroyuki Yoshida , Takayuki Niuya , Toshiyuki Nagata , Yoichi Miyai , Yoshihiro Ogata
发明人： Hiroyuki Yoshida , Takayuki Niuya , Toshiyuki Nagata , Yoichi Miyai , Yoshihiro Ogata
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/92 , H01L29/76
CPC分类号： H01L27/10861 , H01L27/10829 , H01L28/40
摘要： A dynamic RAM in which a groove (20) is formed on the main surface of a semiconductor substrate; a highly concentrated semiconductor layer (80) having one conductive type is formed inside the groove (20) to a depth sufficient to contain the first and second impurity diffusion areas (53) and (22), which are formed on the top of this groove and have the opposite conductive type; a capacitor C.sub.1 formed inside the groove (20), while a transfer gate Tr.sub.1 is formed on the highly concentrated semiconductor layer (80); and the diffusion area (53) is used to connect them.
摘要翻译：一种动态RAM，其中在半导体衬底的主表面上形成有沟槽（20）; 在凹槽（20）的内部形成有一个具有一种导电类型的高度集中的半导体层（80），其深度足以容纳形成在该槽的顶部上的第一和第二杂质扩散区域（53）和（22）并具有相反的导电类型; 形成在所述槽（20）内部的电容器C1，同时在所述高度集中的半导体层（80）上形成传输门Tr1。并且扩散区域（53）用于连接它们。

2. 发明授权

US5470778A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5470778A
公开(公告)日：1995-11-28
申请号：US251866
申请日：1994-05-31
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
IPC分类号： H01L21/205 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).
摘要翻译：一种半导体器件，其中沟槽形沟槽（20）和凹陷（100）形成为在半导体衬底的一侧上是连续的其中上述凹槽和上述凹陷掩埋有多晶硅导电层（103），其导电层的顶部被转换成绝缘体（102），其绝缘膜（102）的底部包含在凹陷（100）中，。

3. 发明授权

US5317177A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5317177A
公开(公告)日：1994-05-31
申请号：US889323
申请日：1992-05-27
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
IPC分类号： H01L21/205 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.
摘要翻译：一种半导体器件，其中沟槽形沟槽（20）和凹陷（100）形成为在半导体衬底的一侧上是连续的其中上述凹槽和上述凹陷掩埋有多晶硅导电层（103），其导电层的顶部被转换成绝缘体（102），其绝缘膜（102）的底部包含在凹部（100）中，。可以根据设计形成元件区域，并且还可以在导电层中没有线切割的同时使表面变平。

4. 发明授权

US06797563B2 Method of forming cross point type DRAM cell 有权
标题翻译：形成交叉点型DRAM单元的方法
公开(公告)号：US06797563B2
公开(公告)日：2004-09-28
申请号：US10348239
申请日：2003-01-21
申请人： Yoichi Miyai , Hiroyuki Yoshida
发明人： Yoichi Miyai , Hiroyuki Yoshida
IPC分类号： H01L21336
CPC分类号： H01L27/10855 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/945
摘要： A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing. A method for manufacturing such a device is also disclosed, and requires only four masks.
摘要翻译：动态随机存取存储器（DRAM）器件包括衬底，多个基本平行的字线和多个基本上平行的位线。在字线和位线的交点处形成多个存储单元。每个存储单元包括从衬底向外延伸的半导体材料的柱。存储节点插头从存储节点经由柱延伸到存储节点接触件和MOS晶体管的漏极和源极之一。位线插头从位线向内延伸到柱的外表面以形成位线接触，并且MOS晶体管的漏极和源极中的另一个。字线插头从字线延伸通过柱，并且字线插头的一部分形成MOS晶体管的栅极。存储节点插头，位线插头和字线插头可以不对称地形成为具有期望的厚度的基本上固体的单一结构，以便于制造。还公开了一种用于制造这种装置的方法，并且仅需要四个掩模。

5. 发明授权

US06563155B2 Cross point type DRAM cell composed of a pillar having an active region 有权
标题翻译：由具有活性区域的柱构成的交叉点型DRAM单元
公开(公告)号：US06563155B2
公开(公告)日：2003-05-13
申请号：US09392133
申请日：1999-09-08
申请人： Yoichi Miyai , Hiroyuki Yoshida
发明人： Yoichi Miyai , Hiroyuki Yoshida
IPC分类号： H01L29108
CPC分类号： H01L27/10855 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/945
摘要： A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing. A method for manufacturing such a device is also disclosed, and requires only four masks.
摘要翻译：动态随机存取存储器（DRAM）器件包括衬底，多个基本平行的字线和多个基本上平行的位线。在字线和位线的交点处形成多个存储单元。每个存储单元包括从衬底向外延伸的半导体材料的柱。存储节点插头从存储节点经由柱延伸到存储节点接触件和MOS晶体管的漏极和源极之一。位线插头从位线向内延伸到柱的外表面以形成位线接触，并且MOS晶体管的漏极和源极中的另一个。字线插头从字线延伸通过柱，并且字线插头的一部分形成MOS晶体管的栅极。存储节点插头，位线插头和字线插头可以不对称地形成为具有期望的厚度的基本上固体的单一结构，以便于制造。还公开了一种用于制造这种装置的方法，并且仅需要四个掩模。

6. 发明授权

US06291293B1 Method for fabricating an open can-type stacked capacitor on an uneven surface 有权
标题翻译：在不平坦表面上制造开罐式叠层电容器的方法
公开(公告)号：US06291293B1
公开(公告)日：2001-09-18
申请号：US09373484
申请日：1999-08-12
申请人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku , Toshiyuki Nagata
发明人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku , Toshiyuki Nagata
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L28/92
摘要： An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 202) of a first electrode (70, 170, 200) is formed by removing a predetermined thickness (66, 166) of at least part of the conductive layer (30, 130). The base (72, 172, 202) is made of a portion of the conductive layer (30, 130) underlying the step (50, 150) by the predetermined thickness (66, 166). A sidewall (74, 174) of the first electrode (70, 170, 200) is formed. A dielectric layer (80) is formed outwardly of the first electrode (70, 170, 200). A second electrode (82) of the capacitor is formed outwardly of the dielectric layer (80).
摘要翻译：通过在基本上不平坦的表面（12,112）外部形成导电层（30,130）来制造开放式罐式叠层电容器。在导电层（30,130）的外表面（32,132）中形成台阶（50,150）。通过去除导电层（30,130）的至少一部分的预定厚度（66,166）来形成第一电极（70,170,200）的基底（72,172,202）。基座（72,172,202）由位于台阶（50,150）下方的预定厚度（66,166）的导电层（30,130）的一部分制成。第一电极（70,170,200）的侧壁（74,174）形成。介电层（80）形成在第一电极（70,170,200）的外侧。电容器的第二电极（82）形成在电介质层（80）的外侧。

7. 发明授权

US06204118B1 Method for fabrication an open can-type stacked capacitor on local topology 有权
标题翻译：本地拓扑结构的开式罐式叠层电容器的制造方法
公开(公告)号：US06204118B1
公开(公告)日：2001-03-20
申请号：US09373214
申请日：1999-08-12
申请人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku
发明人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku
IPC分类号： H01L218242
CPC分类号： H01L28/92 , H01L27/10852
摘要： An open can-type stacked capacitor is fabricated on local topology by forming a conductive layer (30) outwardly of an insulator (14, 86) and an access line (16, 18) extending from the insulator (14, 86). A mask (40) is formed outwardly of the conductive layer (30). A first electrode (50, 80) is formed by removing at least part of the conductive layer (30) exposed by the mask (40). The first electrode (50, 80) includes an annular sidewall (52) having a first segment (54, 82) disposed on the insulator (14, 86) and a second, opposite segment (56) disposed on the access line (16, 18). A dielectric layer (60) is formed outwardly of the first electrode (50, 80). A second electrode (62) is formed outwardly of the dielectric layer (60).
摘要翻译：通过在绝缘体（14,86）之外形成导电层（30）和从绝缘体（14,86）延伸的接入线（16,18），在局部拓扑上制造开放式罐式叠层电容器。在导电层（30）的外侧形成掩模（40）。通过去除由掩模（40）暴露的导电层（30）的至少一部分来形成第一电极（50,80）。第一电极（50,80）包括环形侧壁（52），其具有设置在绝缘体（14,86）上的第一段（54,82）和设置在接入线（16）上的第二相对的段（56） 18）。电介质层（60）形成在第一电极（50,80）的外侧。第二电极（62）形成在电介质层（60）的外侧。

8. 发明授权

US5734184A DRAM COB bit line and moat arrangement 失效
标题翻译： DRAM COB位线和护城河布置
公开(公告)号：US5734184A
公开(公告)日：1998-03-31
申请号：US770883
申请日：1996-12-20
申请人： Katsuyoshi Andoh , Yoichi Miyai , Masayuki Moroi , Katsushi Boku
发明人： Katsuyoshi Andoh , Yoichi Miyai , Masayuki Moroi , Katsushi Boku
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829
摘要： A DRAM uses arcuate moats 18 and wavy bit lines 28, 30 for the array of memory cells. A bit line contact 20 occurs at the apex of the moat and storage node contacts 22, 24 occur at the ends of legs 40, 42 extending from the apex. The wavy bit lines have alternating crests 32, 36 and troughs 34, 38. The bit lines are arranged over the moats with the troughs of each bit line overlying and contacting the apexes of each moat and the crests avoiding any moat. The crests and troughs of the bit lines are offset from one another. In a half-pitch pattern, the troughs of one bit line lie adjacent to the crests of the next bit line. The moats are concave between the legs and the angle between the legs is between about 140 and 170 degrees. The angle between the crests and troughs of the bit lines is between about 110 and 160 degrees. In one embodiment, the central portion 70 between the areas surrounding the storage node contacts is about 10% wider than the areas surrounding the storage node contacts.
摘要翻译： DRAM对于存储器单元阵列使用弧形护城河18和波纹位线28,30。位线接触20发生在护城河的顶点处，并且存储节点接触件22,24发生在从顶点延伸的腿部40,42的端部处。波纹位线具有交替的峰32,36和槽34,38。位线布置在护城河上，每个位线的槽谷覆盖并接触每个护城河的顶点并且避免任何护城河。位线的波峰和波谷彼此偏移。在半间距图案中，一个位线的槽与下一位线的波峰相邻。护城河两腿之间是凹的，腿之间的角度在大约140和170度之间。位线的波峰和波谷之间的角度在约110和160度之间。在一个实施例中，围绕存储节点触点的区域之间的中心部分70比围绕存储节点触点的区域宽约10％。

9. 发明授权

US5641701A Method for fabricating a semiconductor device with laser programable fuses 失效
标题翻译：用激光可编程保险丝制造半导体器件的方法
公开(公告)号：US5641701A
公开(公告)日：1997-06-24
申请号：US413291
申请日：1995-03-30
申请人： Hideyuki Fukuhara , Yoichi Miyai , David J. McElroy
发明人： Hideyuki Fukuhara , Yoichi Miyai , David J. McElroy
IPC分类号： H01L21/302 , H01L21/461 , H01L21/768 , H01L21/82 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L21/76886 , H01L2224/48463
摘要： A method for fabricating a semiconductor device includes the steps of: forming fuses (40) and conductive pads (46) above a semiconductor substrate (43); depositing a layer of cap oxide (44) over the fuses and the conductive pads; sintering the cap oxide; etching back the layer of cap oxide until the top surface of an insulator (42) over the fuses and the top surfaces of the conductive pads are exposed; performing electrical tests (48) by way of the conductive pads; trimming (50) at least a part of the fuses with a laser beam; depositing a silicon nitride layer (52) overall; depositing a mask coating over the silicon nitride; patterning the mask coating (54) to expose the conductive pads; and etching the mask coating and the silicon nitride layer to expose the conductive pads.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底（43）的上方形成熔丝（40）和导电焊盘（46）; 在保险丝和导电垫上方沉积一层氧化碳（44）; 烧结氧化膜; 蚀刻覆盖氧化物层，直到熔丝上方的绝缘体（42）的顶表面和导电焊盘的顶表面露出; 通过导电垫执行电测试（48）; 用激光束修剪（50）至少一部分保险丝; 整个沉积氮化硅层（52）; 在氮化硅上沉积掩模涂层; 图案化掩模涂层（54）以暴露导电焊盘; 并蚀刻掩模涂层和氮化硅层以暴露导电焊盘。

10. 发明授权

US5610100A Method for concurrently forming holes for interconnection between different conductive layers and a substrate element or circuit element close to the substrate surface 失效
标题翻译：用于同时形成用于不同导电层之间的互连的孔和靠近衬底表面的衬底元件或电路元件的方法
公开(公告)号：US5610100A
公开(公告)日：1997-03-11
申请号：US421708
申请日：1995-04-13
申请人： Hiroyuki Kurino , Yoichi Miyai
发明人： Hiroyuki Kurino , Yoichi Miyai
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/768
摘要： In a semiconductor device having conductive paths for electrically coupling a substrate surface with a second conductive/wiring layer, the substrate and the second conductive layer having a first conductive layer therebetween, a second insulating layer separating the first and the second conductive/wiring layers is replaced by a process for forming a protective covering over the patterned and etched first conductive layer. The second conductive layer will provide an electrical contact with the exposed conducting material in the contact holes without the critical patterning and etching process steps typically required when the second insulating layer is formed.
摘要翻译：在具有用于将衬底表面与第二导电/布线层电耦合的导电路径的半导体器件中，衬底和第二导电层之间具有第一导电层，分离第一和第二导电/布线层的第二绝缘层是由用于在图案化和蚀刻的第一导电层上形成保护性覆盖物的方法代替。第二导电层将在接触孔中提供与暴露的导电材料的电接触，而不需要在形成第二绝缘层时通常需要的临界图案化和蚀刻工艺步骤。

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