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1. 发明申请

US20070100586A1 Direct fault diagnostics using per-pattern compactor signatures 有权
标题翻译：直接故障诊断使用每模式压实机签名
公开(公告)号：US20070100586A1
公开(公告)日：2007-05-03
申请号：US11584038
申请日：2006-10-20
申请人： Wu-Tung Cheng , Manish Sharma , Thomas Rinderknecht
发明人： Wu-Tung Cheng , Manish Sharma , Thomas Rinderknecht
IPC分类号： G06F11/30
CPC分类号： G01R31/318547 , G01R31/318357
摘要： In embodiments of the disclosed technology, diagnosis of a circuit is performed using compactor signatures (a technique referred to herein as “signature-based diagnosis”). Signature-based diagnosis typically does not require a test step that bypasses the compactor. Compactor signatures can be read from a compactor on a per-pattern basis, and an expected signature can be loaded into a compactor while an actual signature is being read from the compactor. Error functions can be used to describe relationships between errors in scan cell values and per-pattern compactor signatures, and the functions can be used to help generate a list of fault candidates in a circuit design.
摘要翻译：在所公开的技术的实施例中，使用压缩机签名（本文称为“基于签名的诊断”的技术）来执行电路的诊断。基于签名的诊断通常不需要绕过压实机的测试步骤。压缩机签名可以在每个模式的基础上从压实机读取，并且预期的签名可以加载到压实机中，同时从压实机读取实际的签名。错误函数可用于描述扫描单元格值和每图案压缩器签名中的错误之间的关系，并且该函数可用于帮助生成电路设计中的故障候选列表。

2. 发明申请

US20110179326A1 The Performance Of Signature-Based Diagnosis For Logic BIST 有权
标题翻译：基于签名的逻辑BIST诊断性能
公开(公告)号：US20110179326A1
公开(公告)日：2011-07-21
申请号：US12918988
申请日：2009-02-23
申请人： Manish Sharma , Wu-Tung Cheng , Thomas Rinderknecht
发明人： Manish Sharma , Wu-Tung Cheng , Thomas Rinderknecht
IPC分类号： G01R31/3183 , G06F11/25
CPC分类号： G06F11/277 , G01R31/318547
摘要： Techniques are disclosed for reducing the set of initial candidates in signature based diagnosis methodology. These techniques are based on a unique way of making optimum use of information from logic back-cone tracing along with equations that describe the test response compactor.
摘要翻译：公开了用于减少基于签名的诊断方法中的初始候选者的集合的技术。这些技术基于一种独特的方式，从逻辑后锥跟踪中最佳地利用信息以及描述测试响应压实器的方程式。

3. 发明申请

US20050081130A1 Using constrained scan cells to test integrated circuits 有权
标题翻译：使用受限扫描单元测试集成电路
公开(公告)号：US20050081130A1
公开(公告)日：2005-04-14
申请号：US10961760
申请日：2004-10-07
申请人： Thomas Rinderknecht , Wu-Tung Cheng
发明人： Thomas Rinderknecht , Wu-Tung Cheng
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318547
摘要： Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.
摘要翻译：公开了用于测试集成电路的各种新的和非显而易见的装置和方法。在一个示例性实施例中，在集成电路设计中选择控制点。识别集成电路设计中的扫描单元，其可以加载一组固定值，以将期望的测试值传播到控制点。集成电路设计被修改为包括配置成在测试阶段期间以集合的固定值在集成电路设计中加载扫描单元的电路组件。可以通过将控制点对准扫描单元来识别一个或多个扫描单元，从而确定扫描单元必须输出的值，以便将控制点驱动到期望的测试值。还公开了包括计算机可执行指令的计算机可读介质，所述计算机可执行指令用于使计算机执行任何所公开的方法或任何所公开的设备的计算机可读设计信息。

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