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1. 发明授权

US5970332A Method of manufacturing a semiconductor device with a BiCMOS circuit 失效
标题翻译：用BiCMOS电路制造半导体器件的方法
公开(公告)号：US5970332A
公开(公告)日：1999-10-19
申请号：US623384
申请日：1996-03-27
申请人： Armand Pruijmboom , Alexander C. L. Jansen , Ronald Koster , Willem Van Der Wel
发明人： Armand Pruijmboom , Alexander C. L. Jansen , Ronald Koster , Willem Van Der Wel
IPC分类号： H01L29/43 , H01L21/28 , H01L21/8249 , H01L27/06 , H01L29/78 , H01L21/8238
CPC分类号： H01L21/8249
摘要： A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is destined for the bipolar transistor and a second region (7) for the MOS transistor. The second region is provided with a gate dielectric (10). Then an electrode layer of non-crystalline silicon (11) is provided on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode (12) is formed on the first region and a gate electrode (13) on the second region. The electrode layer is provided with a doping by means of a treatment whereby a first dopant is provided at the area of the first region and a second dopant at the area of the second region, the first dopant being provided to a concentration such that the emitter zone of the transistor can be formed through diffusion from the emitter electrode to be formed in the electrode layer, while the second dopant is provided to a concentration lower than that of the first dopant. Owing to the comparatively low doping level, gate oxide breakdown is prevented during plasma etching and ion implantation.
摘要翻译：制造具有双极晶体管（1）的半导体器件的方法和形成在硅体（3）中的MOS晶体管（2），为此目的，提供了一种场致绝缘区域（4） 7）邻接所述主体的表面（5）是相互绝缘的。第一区域（6）用于双极晶体管和用于MOS晶体管的第二区域（7）。第二区域设置有栅极电介质（10）。然后在表面上提供非晶硅（11）的电极层，该电极层设置有掺杂，并且其中电极层随后在第一区域上形成发射电极（12），栅电极（13））在第二个地区。电极层通过处理被提供掺杂，由此在第一区域的区域处提供第一掺杂剂，在第二区域的区域设置第二掺杂剂，第一掺杂剂被提供为使得发射极晶体管的区域可以通过从要在电极层中形成的发射极电极的扩散而形成，而第二掺杂剂的浓度比第一掺杂剂的浓度低。由于相对较低的掺杂水平，在等离子体蚀刻和离子注入期间防止栅氧化层击穿。

2. 发明授权

US5824560A Method of manufacturing a semiconductor device with BICMOS circuit 失效
标题翻译：使用BICMOS电路制造半导体器件的方法
公开(公告)号：US5824560A
公开(公告)日：1998-10-20
申请号：US623383
申请日：1996-03-27
申请人： Willem Van Der Wel , Alexander C. L. Jansen , Ronald Koster , Armand Pruijmboom
发明人： Willem Van Der Wel , Alexander C. L. Jansen , Ronald Koster , Armand Pruijmboom
IPC分类号： H01L29/43 , H01L21/28 , H01L21/8249 , H01L27/06 , H01L29/78 , H01L21/265
CPC分类号： H01L21/8249 , Y10S148/009
摘要： A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is to be used for the bipolar transistor and a second region for the MOS transistor. The two regions are provided in that order with a gate dielectric layer (10) and an auxiliary layer (11) of non-crystalline silicon. The auxiliary layer and the gate dielectric layer are subsequently removed from the first region. Then an electrode layer (13) of non-crystalline silicon is deposited. An emitter electrode (15) is formed in the electrode layer on the first region, and a gate electrode (16) is formed both in the electrode layer and in the auxiliary layer on the second region. The electrode layer is subjected to a treatment whereby non-crystalline silicon is removed and whereby a layer of non-crystalline silicon is formed on the surface of the silicon body which has substantially the same thickness at the area of the first region and at the area of the second region. Overetching of the base zone (9) in the formation of the emitter is avoided thereby, so that the base zone may be comparatively thin.
摘要翻译：制造具有双极晶体管（1）的半导体器件的方法和形成在硅体（3）中的MOS晶体管（2），为此目的，提供了一种场致绝缘区域（4） 7）邻接所述主体的表面（5）是相互绝缘的。第一区域（6）将用于双极晶体管和用于MOS晶体管的第二区域。这两个区域依次具有栅极电介质层（10）和非结晶硅的辅助层（11）。随后从第一区域去除辅助层和栅极电介质层。然后沉积非晶硅的电极层（13）。在第一区域的电极层中形成发射电极（15），在第二区域的电极层和辅助层中形成栅电极（16）。对电极层进行处理，由此去除非晶硅，由此在硅体的表面上形成非晶硅层，该层在第一区域的区域处具有基本相同的厚度的第二个地区。因此避免了形成发射器的基区（9）的过蚀刻，使得基区可以相对较薄。

3. 发明授权

US5508213A Method of manufacturing a semiconductor device in which a semiconductor zone is formed through diffusion from a strip of polycrystalline silicon 失效
标题翻译：制造半导体器件的方法，其中通过从多晶硅条带扩散形成半导体区
公开(公告)号：US5508213A
公开(公告)日：1996-04-16
申请号：US326440
申请日：1994-10-20
申请人： Willem Van Der Wel , Alexander C. L. Jansen , Ronald Koster
发明人： Willem Van Der Wel , Alexander C. L. Jansen , Ronald Koster
IPC分类号： H01L29/73 , H01L21/225 , H01L21/285 , H01L21/306 , H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/28525 , Y10S148/009
摘要： A method of manufacturing a semiconductor device whereby on a surface (3) of a semiconductor body (1) a conductor track (21) of polycrystalline silicon insulated from the surface (3) is provided in a layer of doped polycrystalline silicon (11) provided on a layer of insulating material (10), and whereby a strip of polycrystalline silicon (19, 35) is formed between an edge (18) of the conductor (21) and a portion (24, 34) of the surface (3) adjoining the edge (18), after which a semiconductor zone (30) is formed through diffusion of dopant from the conductor (21) through the strip (19, 35) into the semiconductor body (1). During the formation of the insulated conductor (21) and the strip of polycrystalline silicon (19, 35), a window (15) is etched into the layer of polycrystalline silicon (11) by means of a first etching mask (13), after which the insulating layer (10) is removed from the surface (3) within the window (15), the window (15) is provided at its edge (18) with a strip of polycrystalline silicon (19, 35), and the conductor (21) is etched into the layer of polycrystalline silicon (11) by means of a second etching mask (20), this second etching mask (20) covering at least a portion of the edge (18) of the window (15). Further conductors (22, 23) may be formed in the polycrystalline layer (11) next to the insulated conductor (21), all conductors (21, 22, 23) being given dimensions such as defined by the second etching mask (20).
摘要翻译：一种制造半导体器件的方法，其中在半导体本体（1）的与表面（3）绝缘的多晶硅的导体轨道（21）的表面（3）上设置有提供的掺杂多晶硅层（11）在一层绝缘材料（10）上，并且由此在导体（21）的边缘（18）和表面（3）的部分（24,34）之间形成多晶硅条（19,35）邻接边缘（18），之后通过掺杂剂从导体（21）穿过条带（19,35）扩散到半导体本体（1）中而形成半导体区域（30）。在形成绝缘导体（21）和多晶硅条（19,35）期间，通过第一蚀刻掩模（13）将窗口（15）蚀刻到多晶硅层（11）中，之后其中绝缘层（10）从窗口（15）内的表面（3）移除，窗口（15）在其边缘（18）处设置有多晶硅条（19,35），并且导体（21）通过第二蚀刻掩模（20）蚀刻到多晶硅层（11）中，该第二蚀刻掩模（20）覆盖窗口（15）的边缘（18）的至少一部分。另外的导体（22,23）可以形成在绝缘导体（21）旁边的多晶层（11）中，所有的导体（21,22,23）都具有由第二蚀刻掩模（20）限定的尺寸。

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