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1. 发明授权

US06646949B1 Word line driver for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的字线驱动
公开(公告)号：US06646949B1
公开(公告)日：2003-11-11
申请号：US09537498
申请日：2000-03-29
申请人： Wayne F. Ellis , Louis L-C. Hsu , Jack A. Mandelman , William R. Tonti
发明人： Wayne F. Ellis , Louis L-C. Hsu , Jack A. Mandelman , William R. Tonti
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line for a row of memory elements of a dynamic random access memory. A first transistor is connected to a source of negative potential and to the word line for switching the word line to a source of negative potential in response to a decoder signal. A diode is additionally connected to the word line and to a selector signal. A second transistor applies a positive potential to the word line in response to a decoder signal. The word line is charged to a positive potential. The word line is reset to a substantially negative potential in two stages. In the first stage, conduction is through the diode to a ground connection which dissipates a majority of the charge of the word line. The remaining charge is dissipated during a second stage when the first transistor discharges the word line remaining charge through a source of negative potential.
摘要翻译：用于动态随机存取存储器的一行存储元件的字线。第一晶体管连接到负电位源和字线，用于响应于解码器信号将字线切换到负电位源。二极管另外连接到字线和选择器信号。第二晶体管响应于解码器信号向字线施加正电位。字线被充电到正电位。字线在两个阶段重置为基本上为负的电位。在第一阶段，传导通过二极管到接地连接，消耗字线的大部分电荷。当第一晶体管通过负电位源将字线剩余电荷放电时，剩余电荷在第二阶段消散。

2. 发明授权

US5981332A Reduced parasitic leakage in semiconductor devices 失效
公开(公告)号：US5981332A
公开(公告)日：1999-11-09
申请号：US940237
申请日：1997-09-30
申请人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
发明人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10829
摘要： A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.

3. 发明授权

US6163045A Reduced parasitic leakage in semiconductor devices 有权
标题翻译：减少半导体器件中的寄生泄漏
公开(公告)号：US6163045A
公开(公告)日：2000-12-19
申请号：US215011
申请日：1998-12-17
申请人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
发明人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829
摘要： A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.
摘要翻译：一种沟槽式电容器，其具有与该套环相邻的扩散区域以增加寄生MOSFET的栅极阈值电压。这使得能够使用更薄的套环，同时仍然实现可接受的泄漏。在一个实施例中，扩散区域是自对准的。

4. 发明授权

US5966339A Programmable/reprogrammable fuse 失效
标题翻译：可编程/可编程保险丝
公开(公告)号：US5966339A
公开(公告)日：1999-10-12
申请号：US88889
申请日：1998-06-02
申请人： Louis L. C. Hsu , Kenneth C. Arndt , Jack A. Mandelman
发明人： Louis L. C. Hsu , Kenneth C. Arndt , Jack A. Mandelman
IPC分类号： G11C17/16 , G11C29/00 , G11C7/00
CPC分类号： G11C29/781 , G11C17/16
摘要： A programmable/reprogrammable fuse arrangement that includes two fuse links provided each with an output port and an exclusive-or gate connected to the output port of each of the two fuses, wherein the fuse arrangement is reprogrammed by successively blowing both of the two fuse links is described. The programmable/reprogrammable fuse arrangement can be extended to a plurality of fuses and cascaded exclusive-ORs such that each fuse link provides one leg of the gate and the previous stage, the second. Thus, for N fuse links and N exclusive-ORs, the fuse arrangement thus formed can be reprogrammed a total of N times by sequentially blowing one fuse link at a time. The arrangement ceases to be reprogrammable once all the fuse links have been blown. The reprogrammable fuse arrangement is of particular importance for semiconductor memories and microprocessors, as for instance, for bringing in-line redundancy units attached to a fuse link.
摘要翻译：一种可编程/可重新编程的熔丝装置，包括两个熔丝链，每个熔断器具有输出端口和连接到两个保险丝中的每一个的输出端口的异或门，其中熔丝装置通过连续地吹送两个熔丝连接被描述。可编程/可重新编程的熔丝布置可以扩展到多个熔丝和级联异或，使得每个熔丝连接提供栅极的一条支脚和前一级，第二级。因此，对于N个熔丝链路和N个异或，由此形成的熔丝装置可以通过一次顺序吹送一个熔丝链而重新编程N次。一旦所有的熔断体熔断，该装置就不再可编程了。可重编程熔丝装置对于半导体存储器和微处理器是特别重要的，例如用于连接到熔丝链路的在线冗余单元。

5. 发明授权

US6049495A Auto-programmable current limiter to control current leakage due to bitline to wordline short 有权
标题翻译：自动可编程限流器，用于控制由于位线到字线短路引起的电流泄漏
公开(公告)号：US6049495A
公开(公告)日：2000-04-11
申请号：US243646
申请日：1999-02-03
申请人： Louis L. C. Hsu , Giuseppe La Rosa , Jack A. Mandelman
发明人： Louis L. C. Hsu , Giuseppe La Rosa , Jack A. Mandelman
IPC分类号： G11C11/404 , G11C29/02 , G11C29/50 , G11C7/00 , G11C16/04
CPC分类号： G11C29/025 , G11C11/404 , G11C29/02 , G11C29/50 , G11C11/401
摘要： A method and structure for disconnecting shorted bitlines from a dynamic random access memory circuit includes supplying a precharge voltage to equalization lines in the integrated circuit, supplying a negative voltage to wordlines in the integrated circuit, activating equalization devices connected to the bitlines and the equalization lines and maintaining the precharge voltage and the negative voltage until a short between one of the bitlines and one of the wordlines causes a corresponding equalization device of the equalization devices to have a permanently elevated threshold voltage.
摘要翻译：用于从动态随机存取存储器电路断开短路位线的方法和结构包括向集成电路中的均衡线提供预充电电压，向集成电路中的字线提供负电压，激活连接到位线和均衡线的均衡器件并且保持预充电电压和负电压，直到位线之一和字线之一之间的短路导致均衡装置的相应均衡装置具有永久升高的阈值电压。

6. 发明申请

US20100230781A1 TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT 有权
标题翻译：用于可编程集成电路的抗融合结构
公开(公告)号：US20100230781A1
公开(公告)日：2010-09-16
申请号：US12537473
申请日：2009-08-07
申请人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.
摘要翻译：沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层沟槽的侧壁。电介质层设置在导电插塞和掺杂区域之间。电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

7. 发明授权

US07656005B2 Electrically programmable π-shaped fuse structures and methods of fabrication thereof 失效
标题翻译：电气可编程的pi形熔丝结构及其制造方法
公开(公告)号：US07656005B2
公开(公告)日：2010-02-02
申请号：US11768254
申请日：2007-06-26
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

8. 发明授权

US07545253B2 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US07545253B2
公开(公告)日：2009-06-09
申请号：US12128100
申请日：2008-05-28
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
IPC分类号： H01H85/08 , H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

9. 发明授权

US07531388B2 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof 失效
标题翻译：具有窄宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法
公开(公告)号：US07531388B2
公开(公告)日：2009-05-12
申请号：US11876942
申请日：2007-10-23
申请人： Roger A. Booth, Jr. , William R. Tonti , Jack A. Mandelman
发明人： Roger A. Booth, Jr. , William R. Tonti , Jack A. Mandelman
IPC分类号： H01L21/82 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

10. 发明授权

US07460003B2 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US07460003B2
公开(公告)日：2008-12-02
申请号：US11372387
申请日：2006-03-09
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
IPC分类号： H01H85/08 , H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

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