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1. 发明授权

US06999365B2 Semiconductor memory device and current mirror circuit 失效
标题翻译：半导体存储器件和电流镜电路
公开(公告)号：US06999365B2
公开(公告)日：2006-02-14
申请号：US10896701
申请日：2004-07-22
申请人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
发明人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C16/28
摘要： A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.
摘要翻译：使用能够降低电源电压的读出放大器电路来提供半导体存储器件。半导体存储器件包括存储单元阵列，每个存储器单元被配置为根据电流的存在/不存在或大小来存储数据; 感测放大器，被配置为基于从存储器单元阵列中选择的存储器单元中的数据与施加到参考感测线的参考电压比较在感测线上引起的电压以确定数据; 以及参考电压发生器，被配置为产生施加到参考感测线的参考电压。

2. 发明授权

US06788601B2 Semiconductor memory device and current mirror circuit 失效
标题翻译：半导体存储器件和电流镜电路
公开(公告)号：US06788601B2
公开(公告)日：2004-09-07
申请号：US10305785
申请日：2002-11-26
申请人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
发明人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C16/28
摘要： A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.
摘要翻译：一种半导体存储器件包括存储单元阵列，一个读出放大器，和一个基准电压generator.The参考电压发生器包括含有参考单元中流动的基准电流和第一电流源负载提供电流的基准的基准电池单元细胞; 含有参考晶体管的参考晶体管单元中流动反射基准电流和供给电流的参考晶体管的第二电流源负载的电流; 用于参考晶体管的负反馈控制的控制放大器; 电流源晶体管; 以及连接到参考感测线的第三电流源负载。

3. 发明授权

US06807097B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06807097B2
公开(公告)日：2004-10-19
申请号：US10661571
申请日：2003-09-15
申请人： Yoshinori Takano , Tadayuki Taura , Toru Tanzawa
发明人： Yoshinori Takano , Tadayuki Taura , Toru Tanzawa
IPC分类号： G11C1604
CPC分类号： G11C16/3472 , G11C11/5621 , G11C11/5642 , G11C16/28 , G11C16/3436 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.
摘要翻译：非挥发性半导体存储器件包括：每个具有带控制栅极的晶体管结构的电可重写非易失性数据存储单元的阵列; 参考电流源电路，被配置为生成适于在普通读取操作期间使用的第一参考电流和用于在写入和擦除事件之一中的数据状态验证的验证读取操作期间使用的第二参考电流; 读出放大器，被配置为将普通读取操作期间所选择的所选存储单元的读取电流与验证读取操作分别与第一和第二参考电流进行比较，从而执行数据检测; 以及驱动器，被配置为向在普通读取操作和验证读取操作期间当前选择的所选择的存储器单元的控制栅极提供相同的电压。

4. 发明授权

US06552936B2 Semiconductor storage apparatus 失效
公开(公告)号：US06552936B2
公开(公告)日：2003-04-22
申请号：US10052303
申请日：2002-01-18
申请人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
发明人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
IPC分类号： G11C1604
CPC分类号： G11C7/1021 , G11C8/10
摘要： There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

5. 发明授权

US06842377B2 Nonvolatile semiconductor memory device with first and second read modes 失效
标题翻译：具有第一和第二读取模式的非易失性半导体存储器件
公开(公告)号：US06842377B2
公开(公告)日：2005-01-11
申请号：US10412646
申请日：2003-04-11
申请人： Yoshinori Takano , Yasuhiko Honda , Toru Tanzawa , Masao Kuriyama
发明人： Yoshinori Takano , Yasuhiko Honda , Toru Tanzawa , Masao Kuriyama
IPC分类号： G11C16/02 , G11C7/10 , G11C7/22 , G11C16/06 , G11C16/26 , G11C16/28
CPC分类号： G11C7/22 , G11C7/1021 , G11C16/26 , G11C16/28 , G11C2207/2281
摘要： A nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal.
摘要翻译：提供了一种具有可切换地构建的多个读取模式的非易失性半导体存储器件。这种非易失性半导体存储器件是具有其中布置有电可重写非易失性存储单元的存储单元阵列，以及执行存储单元阵列的数据读出的读电路。非易失性半导体存储器件具有第一读取模式和第二读取模式。第一读取模式是通过从存储单元阵列通过读取电路向多于一个的外部端子发送数据时，通过相同位数的并行数据传输来读取数据。第二读取模式用于在将数据从存储器单元阵列发送到读取电路时执行比第一读取模式更大位数的并行数据传输，同时在发送数据时执行比位数更小位数的数据传输从读取电路到外部端子。

6. 发明申请

US20050002252A1 Semiconductor memory device and current mirror circuit 失效
标题翻译：半导体存储器件和电流镜电路
公开(公告)号：US20050002252A1
公开(公告)日：2005-01-06
申请号：US10896701
申请日：2004-07-22
申请人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
发明人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
IPC分类号： G11C16/06 , G11C7/06 , G11C7/14 , G11C16/28 , G11C7/02
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C16/28
摘要： A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.
摘要翻译：半导体存储器件包括存储单元阵列，感测放大器和参考电压发生器。参考电压发生器包括参考单元单元，其包含用于流过参考电流的参考单元和第一电流源负载以向参考单元提供电流; 参考晶体管单元，其包含用于流过反映参考电流的电流的参考晶体管和第二电流源负载以向参考晶体管提供电流; 用于参考晶体管的负反馈控制的控制放大器; 电流源晶体管; 以及连接到参考感测线的第三电流源负载。

7. 发明授权

US06826068B1 Fast data readout semiconductor storage apparatus 失效
标题翻译：快速数据读出半导体存储装置
公开(公告)号：US06826068B1
公开(公告)日：2004-11-30
申请号：US10654463
申请日：2003-09-03
申请人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
发明人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
IPC分类号： G11C506
CPC分类号： G11C7/1021 , G11C8/10
摘要： A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.
摘要翻译：半导体集成电路器件包括第一至第四位线和冗余位线，第一至第四列栅极晶体管和耦合到第一至第四位线和冗余位线中的每一个的冗余列栅极晶体管，第一至第四列选择线路以及耦合到第一至第四列栅极晶体管和冗余列栅极晶体管中的每一个的冗余列选择线。第二列选择线通过第一位线。第三列选择线通过第一和第二位线。第四列选择线通过第一，第二和第三位线。冗余列选择线通过第一，第二，第三和第四位线。

8. 发明授权

US06535427B1 Nonvolatile semiconductor memory device with initialization circuit and control method thereof 失效
标题翻译：具有初始化电路的非易失性半导体存储器件及其控制方法
公开(公告)号：US06535427B1
公开(公告)日：2003-03-18
申请号：US09707983
申请日：2000-11-08
申请人： Yoshinori Takano , Toru Tanzawa , Tadayuki Taura
发明人： Yoshinori Takano , Toru Tanzawa , Tadayuki Taura
IPC分类号： G11C1626
CPC分类号： G11C7/12 , G11C7/20 , G11C16/24 , G11C16/26
摘要： A memory cell is connected to a cell-based bit line. The cell-based bit line is connected to a bit line via a Y decoder. The bit line is connected to a sense bit line via a separation circuit. This sense bit line is connected to a sense line via a bias circuit. An amplifier circuit amplifies a signal voltage on the sense line together with a reference voltage for sensing data. The sense line is connected with a sense line initialization circuit for setting the sense line to a specified voltage. The bit line is connected with a bit line initialization circuit for setting the bit line to a specified voltage. Both the sense line initialization circuit and the bit line initialization circuit are activated in a given period before the amplifier circuit operates to sense data. Thus, the sense line and the bit line are set to specified voltages.
摘要翻译：存储单元连接到基于单元的位线。基于单元的位线通过Y解码器连接到位线。位线通过分离电路连接到感测位线。该感测位线通过偏置电路连接到感测线。放大器电路将感测线上的信号电压与用于感测数据的参考电压一起放大。感测线与感测线初始化电路连接，用于将感测线设置为指定电压。位线与位线初始化电路连接，用于将位线设置为指定电压。感测线初始化电路和位线初始化电路在放大器电路操作以感测数据之前的给定时间段内被激活。因此，感测线和位线被设定为规定的电压。

9. 发明授权

US07071771B2 Current difference divider circuit 失效
标题翻译：电流差分电路
公开(公告)号：US07071771B2
公开(公告)日：2006-07-04
申请号：US10954271
申请日：2004-10-01
申请人： Yoshinori Takano , Tadayuki Taura , Toru Tanzawa
发明人： Yoshinori Takano , Tadayuki Taura , Toru Tanzawa
IPC分类号： G05F1/10
CPC分类号： G11C16/3472 , G11C11/5621 , G11C11/5642 , G11C16/28 , G11C16/3436 , G11C16/3481 , G11C2211/5634
摘要： A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.
摘要翻译：提供了具有多个电流源的电流差分电路。分频器电路包括第一电流源，其可操作以产生第一电流，第二电流源，用于产生比第一电流更小幅度的第二电流;以及第三电流源，用于产生其电流等于第一和第二电流之间的差异并且用于产生由其分割产生的第三电流。电路还包括用于产生可通过镜像第二电流而获得的第四电流的第四电流源。将第三和第四电流加在一起以提供第五电流，然后输出。

10. 发明授权

US06734719B2 Constant voltage generation circuit and semiconductor memory device 有权
标题翻译：恒压发生电路和半导体存储器件
公开(公告)号：US06734719B2
公开(公告)日：2004-05-11
申请号：US10238773
申请日：2002-09-11
申请人： Toru Tanzawa , Yoshinori Takano
发明人： Toru Tanzawa , Yoshinori Takano
IPC分类号： G05F110
CPC分类号： G11C5/147
摘要： A constant voltage generating circuit comprising following elements is shown: a first constant current generation circuit including a first transistor and a second transistor, configured to generate a first voltage and a first current as determined by an operating point to be determined depending on a difference in threshold voltage between the first and second transistors; a second constant current generation circuit configured to generate a second current proportional to said first current; and a voltage generation circuit including a third transistor having its gate and drain connected together, configured to generate a second voltage when letting said second current flow in said third transistor.
摘要翻译：示出包括以下元件的恒压产生电路：第一恒流产生电路，包括第一晶体管和第二晶体管，其被配置为产生由操作点确定的第一电压和第一电流，以根据第所述第一和第二晶体管之间的阈值电压;被配置为产生与所述第一电流成比例的第二电流的第二恒定电流产生电路; 以及包括其栅极和漏极连接在一起的第三晶体管的电压产生电路，被配置为当使所述第二电流流过所述第三晶体管时产生第二电压。

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