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1. 发明授权

US06393564B1 Decrypting device 失效
标题翻译：解密设备
公开(公告)号：US06393564B1
公开(公告)日：2002-05-21
申请号：US09163257
申请日：1998-09-29
申请人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
发明人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
IPC分类号： G06F124
CPC分类号： H04L9/0877 , H04L2209/08
摘要： The decrypting device of this invention includes: a decrypting key generation circuit for generating a decrypting key based on first decrypting key information and second decrypting key information; and a decrypting circuit for decrypting encrypted information using the decrypting key, wherein the first decrypting key information is input from outside the decrypting device, and the second decrypting key information is stored inside the decrypting device.
摘要翻译：本发明的解密装置包括：解密密钥生成电路，用于基于第一解密密钥信息和第二解密密钥信息生成解密密钥; 以及解密电路，用于使用解密密钥对加密信息进行解密，其中，从解密装置外部输入第一解密密钥信息，第二解密密钥信息存储在解密装置内。

2. 发明授权

US06732252B2 Memory interface device and memory address generation device 有权
标题翻译：存储器接口设备和存储器地址生成设备
公开(公告)号：US06732252B2
公开(公告)日：2004-05-04
申请号：US10195975
申请日：2002-07-16
申请人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
发明人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
IPC分类号： G06F1200
CPC分类号： G06F9/345 , G06F13/1673 , H04N19/423 , H04N19/61
摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
摘要翻译：本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中。控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号的输出缓冲区。

3. 发明授权

US06453394B2 Memory interface device and memory address generation device 有权
标题翻译：存储器接口设备和存储器地址生成设备
公开(公告)号：US06453394B2
公开(公告)日：2002-09-17
申请号：US09165785
申请日：1998-10-02
申请人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
发明人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
IPC分类号： G06F1200
CPC分类号： G06F9/345 , G06F13/1673 , H04N19/423 , H04N19/61
摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
摘要翻译：本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括8个多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中。控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号的输出缓冲区。

4. 发明授权

US06353460B1 Television receiver, video signal processing device, image processing device and image processing method 失效
标题翻译：电视接收机，视频信号处理装置，图像处理装置及图像处理方法
公开(公告)号：US06353460B1
公开(公告)日：2002-03-05
申请号：US09162740
申请日：1998-09-29
申请人： Kenta Sokawa , Kazuki Ninomiya , Yoichiro Miki , Naoya Tokunaga , Masahiro Tani , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama
发明人： Kenta Sokawa , Kazuki Ninomiya , Yoichiro Miki , Naoya Tokunaga , Masahiro Tani , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama
IPC分类号： H04N327
CPC分类号： H04N7/0122 , H04N5/45 , H04N5/46 , H04N5/907 , H04N7/01 , H04N21/4316 , H04N21/440218 , H04N21/4622
摘要： The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.
摘要翻译：包括能够显示具有本发明的预定显示器的视频信号的显示装置的电视接收机包括：多个视频信号源; 选择电路，用于选择从多个视频信号源输出的多个视频信号之一; 以及用于将由选择电路选择的视频信号的格式转换为预定显示格式的图像处理器，其中从处理器输出的视频信号被提供给显示装置。

5. 发明授权

US6128733A Program loading method and apparatus 有权
标题翻译：程序加载方法和装置
公开(公告)号：US6128733A
公开(公告)日：2000-10-03
申请号：US165574
申请日：1998-10-02
申请人： Hiroshi Miyaguchi , Naoya Tokunaga
发明人： Hiroshi Miyaguchi , Naoya Tokunaga
IPC分类号： G06F9/06 , G06F9/445 , G06F15/177
CPC分类号： G06F9/445
摘要： A method for loading of program data with high speed and efficiency along with eliminating the need for software modification even if changes occur in the storage addresses and data length of the program data stored in the program memory. In order to load program data in a rewritable manner into a number of functional circuits FC0, FC1, . . . , FCn operating in accordance with the supplied program data, a program memory, for example, a ROM 10, a program loader 12, and program designating apparatus, for example, a microprocessor 14, are provided in the system. In the ROM 10, multiple address pointers are stored in specified storage areas, and corresponding sets of program data are stored in the storage locations indicated by the address pointers in such a manner that a first set of program data is stored in the specified storage area which utilizes the address corresponding to the first address pointer as the start storage address, and a second set of program data is stored in the specified storage area which utilizes the address corresponding to the second address pointer as the start storage address.
摘要翻译：一种用于以高速度和高效率加载程序数据的方法，即使存储在程序存储器中的程序数据的存储地址和数据长度发生变化也不需要软件修改。为了将程序数据以可重写的方式加载到多个功能电路FC0，FC1，...中。。。，根据提供的程序数据操作的FCn，在系统中提供程序存储器，例如ROM 10，程序加载器12和程序指定装置，例如微处理器14。在ROM10中，多个地址指针被存储在指定的存储区域中，并且相应的程序数据组被存储在由地址指针指示的存储位置中，使得第一组程序数据被存储在指定的存储区域其利用与第一地址指针相对应的地址作为开始存储地址，并且将第二组程序数据存储在利用与第二地址指针相对应的地址作为起始存储地址的指定存储区域中。

6. 发明授权

US07739320B2 Waveform equalizer, waveform equalization method, and integrated circuit 有权
标题翻译：波形均衡器，波形均衡方法和集成电路
公开(公告)号：US07739320B2
公开(公告)日：2010-06-15
申请号：US11130604
申请日：2005-05-17
申请人： Yoshinobu Matsumura , Naoya Tokunaga
发明人： Yoshinobu Matsumura , Naoya Tokunaga
IPC分类号： G06F17/10
CPC分类号： H04L25/03038 , H04L25/03057 , H04L2025/03382 , H04L2025/03477 , H04L2025/0349 , H04L2025/03617 , H04L2025/03687
摘要： A waveform equalizer includes a filter unit, an error estimation unit, a tap coefficient storage unit, and an update amount calculation unit which includes an intermediate calculation unit and an update amount setting unit. Coefficient update amount ΔCi(n) for an ith tap is calculated according to an equation ΔCi(n)=αi(n)×μ×e(n)×x*(n−i) with the multiplication by αi(n) being performed by the update amount setting unit. Here, 0
摘要翻译：波形均衡器包括滤波器单元，误差估计单元，抽头系数存储单元和包括中间计算单元和更新量设置单元的更新量计算单元。根据等式＆Dgr计算第i个抽头的系数更新量和Dgr; Ci（n）; Ci（n）=αi（n）×μ×e（n）×x *（n-i）乘以αi （n）由更新量设定单元执行。这里，0 <αi（n）＆nlE; 1和αi（n）是与Ci（n-1）单调增加的函数f（Ci（n-1））。

7. 发明授权

US07133481B2 Synchronization detection apparatus 失效
标题翻译：同步检测装置
公开(公告)号：US07133481B2
公开(公告)日：2006-11-07
申请号：US10311638
申请日：2002-04-05
申请人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Kazuaki Suzuki , Kazuya Ueda
发明人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Kazuaki Suzuki , Kazuya Ueda
IPC分类号： H04L7/00
CPC分类号： H04N5/211 , H04H40/18 , H04L7/042 , H04L7/06 , H04L27/02 , H04N5/08
摘要： An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.
摘要翻译：输入信号DT包含符合ATSC标准的片段同步信号。时钟倍增部分111将时钟CK相乘。可切换取样部112从由倍增时钟定义的多个定时点中选择采样点，并对选择的采样点对输入信号DT进行采样。此外，可切换采样部112在同步未建立状态下将采样点从一个切换到另一个。一旦段同步建立，同步检测装置可以保持同步建立状态，直到现场同步检测失败，或者同步检测装置可以在基于位错误率RT在时间方向上移动同步检测信号之后输出同步检测信号的输入信号。

8. 发明授权

US07054395B2 Automatic gain control for digital demodulation apparatus 失效
标题翻译：数字解调装置的自动增益控制
公开(公告)号：US07054395B2
公开(公告)日：2006-05-30
申请号：US09853682
申请日：2001-05-14
申请人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Hiroaki Ozeki , Kazuya Ueda
发明人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Hiroaki Ozeki , Kazuya Ueda
IPC分类号： H04L27/08
CPC分类号： H03G3/3089
摘要： A digital demodulation apparatus automatically controls gain based on a state of receiving a digital modulated signal. The digital demodulation apparatus amplifies a digital modulated signal wave received through the air with the gain automatically controlled so as to have a predetermined amplitude. In the digital demodulation apparatus, a receive level variation detector detects receive level variation, an amount of noise components of the received digital signal wave. A gain controller 15 controls the gain with a receive level variation adaptive control signal based on the detected receive level variation, the amount of noise components.
摘要翻译：数字解调装置根据接收数字调制信号的状态自动控制增益。数字解调装置以自动控制的增益放大通过空气接收的数字调制信号波，以具有预定的幅度。在数字解调装置中，接收电平变化检测器检测接收电平变化，接收的数字信号波的噪声分量的量。增益控制器15基于检测到的接收电平变化，噪声分量的量，利用接收电平变化自适应控制信号来控制增益。

9. 发明授权

US07302021B2 Digital broadcast receiving apparatus 失效
标题翻译：数字广播接收装置
公开(公告)号：US07302021B2
公开(公告)日：2007-11-27
申请号：US09878427
申请日：2001-06-12
申请人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga
发明人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga
IPC分类号： H04L27/08
CPC分类号： H04N5/4446 , H03G3/3068 , H03G3/3089 , H04H40/18 , H04N5/4401 , H04N5/50 , H04N5/52 , H04N21/42607
摘要： In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave with automatically adjusted gain and demodulating the modulated signal wave to a digital signal, a tuner frequency-converts the modulated digital signal wave to generate a first modulated signal. A first automatic gain control amplification unit controls gain of the tuner to make a level of the first modulated signal at a first predetermined level. An A/D converter converts the first modulated signal into a second modulated signal. A demodulator demodulates the second modulated signal to generate a first demodulated digital signal. A second automatic gain control amplifier generates a second demodulated digital signal where frequency fluctuations included in the digital modulated wave are eliminated.
摘要翻译：在一种数字广播接收装置中，用于利用自动调节增益放大接收到的调制数字信号波并将调制信号波解调为数字信号，调谐器对调制数字信号波进行频率转换以产生第一调制信号。第一自动增益控制放大单元控制调谐器的增益使第一调制信号的电平达到第一预定电平。 A / D转换器将第一调制信号转换成第二调制信号。解调器解调第二调制信号以产生第一解调数字信号。第二自动增益控制放大器产生第二解调数字信号，其中消除了数字调制波中包括的频率波动。

10. 发明授权

US07158565B2 Waveform equalizer and shift register 有权
标题翻译：波形均衡器和移位寄存器
公开(公告)号：US07158565B2
公开(公告)日：2007-01-02
申请号：US10409090
申请日：2003-04-09
申请人： Naoya Tokunaga
发明人： Naoya Tokunaga
IPC分类号： H03H7/30 , H03K1/159
CPC分类号： H04L25/03057 , H04L2025/03445
摘要： In a tap 1 in a shift register of a waveform equalizer, data of an input signal is stored in a data storing FF 111. A tap coefficient computing unit 114 calculates a tap coefficient, which is stored in a tap coefficient storing FF 112 and output to an absolute value computing unit 115. The unit 115 obtains the absolute value of the tap coefficient. A comparator 116 compares the absolute value to a threshold value. A masking unit 117 masks and outputs the data from the data storing FF 111 to a multiplier 113 if the absolute value is smaller than the threshold value, while outputting the data from the data storing FF 111 without change if the absolute value is no less than the threshold value. The multiplier 113 multiplies the data of the input signal by the tap coefficient and outputs a signal to an adder 108.
摘要翻译：在波形均衡器的移位寄存器中的抽头1中，输入信号的数据被存储在存储FF 111的数据中。抽头系数计算单元114计算存储在存储FF 112的抽头系数中并输出到绝对值计算单元115的抽头系数。单元115获得抽头系数的绝对值。比较器116将绝对值与阈值进行比较。如果绝对值小于阈值，则掩蔽单元117将数据从存储FF 111的数据存储到乘法器113，同时如果绝对值不小于阈值。乘法器113将输入信号的数据乘以抽头系数，并将信号输出到加法器108。

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