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    • 2. 发明授权
      US5631869A Semiconductor memory unit having overlapping addresses 失效
    • Semiconductor memory unit having overlapping addresses
    • 具有重叠地址的半导体存储器单元
    • US5631869A
    • 1997-05-20
    • US396297
    • 1995-02-28
    • Kazuki Ninomiya , Tomoharu Kawada
    • Kazuki Ninomiya , Tomoharu Kawada
    • G11C8/16 , G11C7/00
    • G11C8/16
    • A memory unit includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, and a plurality of write word lines. An array of memory cells are connected to the read bit lines, the read word lines, the write bit lines, and the write word lines. Each of the memory cells includes at least two input sections, at least two output sections, and a memory element. The output sections are connected to at least two of the read word lines, respectively, and output data from the memory element to one of the read bit lines in response to signals on the read word lines. The input sections are connected to at least two of the write word lines, respectively, and output data from one of the write bit lines into the memory element in response to signals on the write word lines. A plurality of decoders connected to the read word lines decode a read address signal into output signals, respectively, which are fed to the read word lines. A plurality of decoders connected to the write word lines decode a write address signal into output signals, respectively, which are fed to the write word lines.
    • 存储单元包括多个读位线，多个读字线，多个写位线和多个写字线。 存储单元阵列连接到读位线，读字线，写位线和写字线。 每个存储器单元包括至少两个输入部分，至少两个输出部分和存储元件。 输出部分分别连接到读取字线中的至少两个，并且响应于读取的字线上的信号将数据从存储器元件输出到读位线之一。 输入部分分别连接到写入字线中的至少两个，并且响应于写入字线上的信号将数据从写入位线之一输出到存储器元件中。 连接到读字线的多个解码器将读地址信号分别解码为输入到读字线的输出信号。 连接到写入字线的多个解码器分别将写入地址信号解码为输入到写入字线的输出信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5771185A Signal processor capable of sharing common hardware in a plural processing system 失效
    • Signal processor capable of sharing common hardware in a plural processing system
    • 能够在多个处理系统中共享公共硬件的信号处理器
    • US5771185A
    • 1998-06-23
    • US768085
    • 1996-12-16
    • Jiro Miyake , Tamotsu Nishiyama , Katsuya Hasegawa , Kazuki Ninomiya
    • Jiro Miyake , Tamotsu Nishiyama , Katsuya Hasegawa , Kazuki Ninomiya
    • G06F9/46 , G06F15/78 , G06F17/10 , G06F17/15 , G06F7/00 , G06F7/38 , G06F17/00
    • G06F17/15 , G06F15/78 , G06F17/10 , G06F9/3012 , G06F9/462
    • In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected. As a result of such arrangement, a single piece of image processing hardware can be shared between different broadcasting systems as well as between different algorithms.
    • 为了建立能够执行诸如以各种连接方式进行滤波的基本功能的多个运算单元的连接，提供总线开关，其具有与运算单元的输出端连接的多个输入数据线，至少一个外部输入数据 与运算单元的输入端连接的多个输出数据线，以及至少一个外部输出数据线。 此外，提供两个寄存器组，其存储指定由运算单元执行的处理的内容的算术控制信息和指定总线开关内的连接方式的连接控制信息。 根据广播系统，更新由寄存器组中的一个和另一个保存的信息的信息，并且根据处理算法选择两个寄存器组中的任一个。 作为这种安排的结果，可以在不同的广播系统之间以及不同的算法之间共享单个图像处理硬件。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5208783A Memory unit delay-compensating circuit 失效
    • Memory unit delay-compensating circuit
    • 存储单元延迟补偿电路
    • US5208783A
    • 1993-05-04
    • US684735
    • 1991-04-15
    • Kazuki Ninomiya , Seiji Yamaguchi
    • Kazuki Ninomiya , Seiji Yamaguchi
    • G11C8/18
    • G11C8/18
    • A memory unit includes an array of memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A decoder receives an address signal at a timing which follows an occurrence of a clock signal by a given time t1. The address signal is in synchronism with the clock signal. The clock signal has a preset period t0. The decoder decodes the address signal into a word signal and outputs the word signal at a timing which follows the reception of the address signal by a given time t2. A delay device delays the clock signal by a preset time "t" and thereby converts the clock signal into a control signal. An access to a word of the memory cells is performed via one of the word lines in accordance with the word signal at a timing determined by the control signal. The bit lines are precharged at a timing determined by the control signal. The preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0.
    • 存储单元包括存储单元阵列。 字线连接到存储单元。 位线连接到存储单元。 解码器在给定时间t1之后的时钟信号发生的定时接收地址信号。 地址信号与时钟信号同步。 时钟信号具有预设时段t0。 解码器将地址信号解码为字信号，并在接收到地址信号的定时将字信号输出给定时间t2。 延迟装置将时钟信号延迟预设时间“t”，从而将时钟信号转换成控制信号。 在由控制信号确定的定时根据字信号经由一条字线执行对存储器单元的字的访问。 位线在由控制信号确定的定时被预充电。 预设时间“t”比时间t1和t2之和长但小于周期t0的一半。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5777688A Signal processor 失效
    • Signal processor
    • 信号处理器
    • US5777688A
    • 1998-07-07
    • US644784
    • 1996-05-10
    • Jiro Miyake , Kazuki Ninomiya , Miki Urano , Shintaro Tsubata , Tamotsu Nishiyama
    • Jiro Miyake , Kazuki Ninomiya , Miki Urano , Shintaro Tsubata , Tamotsu Nishiyama
    • G06F17/10 , H04N5/14 , H04N5/265 , H04N9/64
    • G06F17/10 , H04N5/14 , H04N5/265
    • A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.
    • 多个信号处理元件被级联连接以形成具有三个信号路径的信号处理器。 信号处理器是一个小型设备，可以通过产品总和的计算和划分来共享。 在每个信号处理元件中，第一和第二移位器和加法器减法器用于执行用于将变量乘以作为乘积和计算的基础的常数的移位加法。 加法器 - 减法器和用于移位由加减法器获得的结果的第三移位器用于执行减法和移位以获得部分商和部分余数除法。 这样获得的部分商通过标志保持电路在下一级传送到信号处理元件。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5703800A Signal processor 失效
    • Signal processor
    • 信号处理器
    • US5703800A
    • 1997-12-30
    • US545204
    • 1995-10-19
    • Kazuki Ninomiya , Keizo Sumida , Jiro Miyake , Tamotsu Nishiyama
    • Kazuki Ninomiya , Keizo Sumida , Jiro Miyake , Tamotsu Nishiyama
    • G06F15/80 , G06F7/38
    • G06F15/8046 , G06F15/8023
    • An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E�(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E�x,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an E�x-1,y! arithmetic cell via a direct bus as well as from an E�x-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.
    • 公开了一种改进的信号处理器，其适用于以较小的总线结构实现并行处理的图像的收敛处理。 提供由能够同时操作的十个算术单元形成的运算阵列。 每个算术单元由列号x为1 的E [（列号），y（行号）]的表示来指定， = 4。 每个算术单元具有用于乘法运算的乘法器和加法器。 由E [x，y]指定的算术单元，其中2
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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