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1. 发明授权

US6141290A Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals 有权
标题翻译：响应于不同步控制信号来控制集成电路的操作的方法和装置
公开(公告)号：US6141290A
公开(公告)日：2000-10-31
申请号：US291414
申请日：1999-04-13
申请人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
发明人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C11/406 , G11C8/00
CPC分类号： G11C11/406
摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.
摘要翻译：只要在生成自动刷新命令之后的预定等待时间段内，自刷新解码器产生自刷新命令，只要时钟使能信号变为低电平即可。结果，即使将与自刷新命令相区别的自动刷新命令的时钟使能控制信号被过度延迟超过对应于自刷新命令和自刷新命令的其他控制信号，SDRAM也能够进入自刷新模式。自刷新解码器包括预先加载等待时间值的计数器，并且响应于自动刷新命令而减小到终端计数以终止等待时间。只要终端计数未达到，计数器的输出被解码以提供使能信号。只要存在使能信号，响应于接收到时钟使能信号而产生自刷新命令。

2. 发明授权

US06310819B1 Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals 有权
标题翻译：响应于不同步控制信号来控制集成电路的操作的方法和装置
公开(公告)号：US06310819B1
公开(公告)日：2001-10-30
申请号：US09703496
申请日：2000-10-31
申请人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
发明人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.
摘要翻译：只要在生成自动刷新命令之后的预定等待时间段内，自刷新解码器产生自刷新命令，只要时钟使能信号变为低电平即可。结果，即使将与自刷新命令相区别的自动刷新命令的时钟使能控制信号被过度延迟超过对应于自刷新命令和自刷新命令的其他控制信号，SDRAM也能够进入自刷新模式。自刷新解码器包括预先加载等待时间值的计数器，并且响应于自动刷新命令而减小到终端计数以终止等待时间。只要终端计数未达到，计数器的输出被解码以提供使能信号。只要存在使能信号，响应于接收到时钟使能信号而产生自刷新命令。

3. 发明授权

US06229749B1 Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals 有权
公开(公告)号：US06229749B1
公开(公告)日：2001-05-08
申请号：US09574678
申请日：2000-05-17
申请人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
发明人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C800
CPC分类号： G11C11/406
摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.

4. 发明授权

US5999481A Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals 失效
公开(公告)号：US5999481A
公开(公告)日：1999-12-07
申请号：US918614
申请日：1997-08-22
申请人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
发明人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.

5. 发明授权

US06512711B1 Synchronous dynamic random access memory device 有权
公开(公告)号：US06512711B1
公开(公告)日：2003-01-28
申请号：US09572820
申请日：2000-05-16
申请人： Jeffrey P. Wright , Hua Zheng
发明人： Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C700
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/109
摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

6. 发明授权

US06365421B2 Method and apparatus for storage of test results within an integrated circuit 失效
标题翻译：在集成电路内存储测试结果的方法和装置
公开(公告)号：US06365421B2
公开(公告)日：2002-04-02
申请号：US09531023
申请日：2000-03-20
申请人： Brett Debenham , Kim Pierce , Douglas J. Cutter , Kurt Beigel , Fan Ho , Patrick J. Mullarkey , Dien Luong , Hua Zheng , Michael Shore , Jeffrey P. Wright , Adrian E. Ong , Todd A. Merritt
发明人： Brett Debenham , Kim Pierce , Douglas J. Cutter , Kurt Beigel , Fan Ho , Patrick J. Mullarkey , Dien Luong , Hua Zheng , Michael Shore , Jeffrey P. Wright , Adrian E. Ong , Todd A. Merritt
IPC分类号： H01L2166
CPC分类号： H01L27/112 , G01R31/31702 , G01R31/3181 , G11C17/10 , G11C17/18
摘要： An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.
摘要翻译：集成电路存储器件具有多个非易失性可编程元件，用于在测试序列中存储所选择的里程碑处的通过/失败状态位。在测试过程的选定点，元件可以被编程以指示设备已经通过与该过程中的所选点相关联的测试。在对设备执行进一步测试之前，读取该元素以验证其在测试过程中通过先前的测试。如果没有编写适当的元素，则设备被拒绝。可以根据先前的测试步骤重新测试被拒绝的设备。激光熔丝，电可编程熔丝或反熔丝用于存储测试结果。使用电可写非易失性存储器元件允许在器件被封装之后对元件进行编程。

7. 发明授权

US06351404B1 Synchronous dynamic random access memory device 有权
公开(公告)号：US06351404B1
公开(公告)日：2002-02-26
申请号：US09572387
申请日：2000-05-16
申请人： Jeffrey P. Wright , Hua Zheng
发明人： Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C502
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/109
摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

8. 发明授权

US06154860A High-speed test system for a memory device 有权
标题翻译：高速测试系统用于存储器件
公开(公告)号：US06154860A
公开(公告)日：2000-11-28
申请号：US321295
申请日：1999-05-27
申请人： Jeffrey P. Wright , Hua Zheng , Paul M. Fuller
发明人： Jeffrey P. Wright , Hua Zheng , Paul M. Fuller
IPC分类号： G01R31/28 , G11C29/00 , G11C29/34 , G11C29/38
CPC分类号： G11C29/38 , G11C29/34
摘要： A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.
摘要翻译：存储器件需要至少两个来自外部测试装置的输入/输出线与其耦合。来自存储器件的第一条DQ线提供了阵列的直接数据路径，以便外部测试器可以以存储器件的最大速度从阵列中读取数据。用于在地址压缩模式期间复用和比较多个DQ线的测试模式电路被耦合到两条或更多条DQ线，包括第一条DQ线。压缩模式测试电路可以包括片上比较器，其比较同时写入存储器件和从存储器件读取的数据。比较电路输出指示从存储器件读取的数据是否匹配的数据测试标志。测试标志通过多路复用器输出到第二个DQ线。因此，可以从第一DQ线测试器件的速度，而可以在第二DQ线上对片上比较的结果进行采样。

9. 发明授权

US6133053A Circuit and a method for configuring pad connections in an integrated device 失效
公开(公告)号：US6133053A
公开(公告)日：2000-10-17
申请号：US115103
申请日：1998-07-13
申请人： Jeffrey P. Wright , Hua Zheng
发明人： Jeffrey P. Wright , Hua Zheng
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G01R31/319 , H01L21/00
CPC分类号： G01R31/2648 , G01R31/318505 , G01R31/318511 , G01R31/31905
摘要： An integrated device includes a configuration circuit that is coupled to first and second bond pads and first and second conductive paths of the integrated device. The circuit receives a map signal that has a first value during a first operational mode of the integrated device and a second value during a second operational mode of the integrated device. In response to the first value, the circuit couples the first pad to the second conductive path. In response to the second value, the circuit couples the first pad to the first conductive path and the second pad to the second conductive path. The first operational mode may be a wafer test mode.

10. 发明授权

US6044027A Circuit and method for providing a substantially constant time delay over a range of supply voltages 有权
标题翻译：电路和方法，用于在电源电压范围内提供基本恒定的时间延迟
公开(公告)号：US6044027A
公开(公告)日：2000-03-28
申请号：US333818
申请日：1999-06-15
申请人： Hua Zheng , Jeffrey P. Wright
发明人： Hua Zheng , Jeffrey P. Wright
IPC分类号： G11C7/10 , G11C7/22 , G11C8/18 , H03K5/13 , H03K5/135 , G11C5/14
CPC分类号： H03K5/133 , G11C7/1072 , G11C7/22 , G11C8/18 , H03K5/135
摘要： A delay circuit provides a substantially constant delay over a range of power-supply voltages. The delay circuit includes an input terminal that receives an input signal, an output terminal that provides an output signal, and a supply terminal that receives a supply voltage. A delay stage is coupled between the input and the output terminals and, when the supply voltage has a predetermined value, generates the output signal a predetermined delay time after it receives the input signal. A control stage is coupled between the supply terminal and the delay stage and regulates the supply current that flows between the supply terminal and the delay stage such that the delay time of the delay stage remains substantially equal to the predetermined delay time as the supply voltage varies from the predetermined value.
摘要翻译：延迟电路在一定范围的电源电压上提供基本恒定的延迟。延迟电路包括接收输入信号的输入端子，提供输出信号的输出端子和接收电源电压的电源端子。延迟级耦合在输入端子和输出端子之间，并且当电源电压具有预定值时，在输入信号接收到输入信号之后产生预定的延迟时间。控制级耦合在电源端子和延迟级之间，并且调节在电源端子和延迟级之间流动的电源电流，使得延迟级的延迟时间保持基本上等于预定延迟时间，因为电源电压变化从预定值。

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