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1. 发明授权

US08895413B2 Monolithic integration of photonics and electronics in CMOS processes 有权
标题翻译：光电子学与电子学在CMOS工艺中的整体集成
公开(公告)号：US08895413B2
公开(公告)日：2014-11-25
申请号：US13364909
申请日：2012-02-02
申请人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
发明人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
IPC分类号： H01L27/12 , H01L21/782 , H01L21/84
CPC分类号： H04B10/2575 , H01L21/84 , H01L27/1203 , H04B10/40
摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.
摘要翻译：公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件，用于光子和电子器件，其结合到每个晶片的至少一部分其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。电子器件可以利用穿硅通孔耦合到光学器件。可以使用选择性区域生长过程来制造不同的厚度。可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。可以利用选择性背面蚀刻来制造包覆层。可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

2. 发明授权

US08877616B2 Method and system for monolithic integration of photonics and electronics in CMOS processes 有权
标题翻译： CMOS工艺中光子学与电子学的单片集成方法与系统
公开(公告)号：US08877616B2
公开(公告)日：2014-11-04
申请号：US12554449
申请日：2009-09-04
申请人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
发明人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
IPC分类号： H01L27/12 , H01L21/782 , H01L21/84
CPC分类号： H04B10/2575 , H01L21/84 , H01L27/1203 , H04B10/40
摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
摘要翻译：公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的单个CMOS晶片上制造光子和电子器件。利用体CMOS工艺和/或利用SOI CMOS工艺的SOI晶片，可以在绝缘体上半导体（SOI）晶片上制造器件。可以使用双重SOI工艺和/或选择性区域生长工艺来制造不同的厚度。可以利用一个或多个氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。可以利用选择性背面蚀刻来制造包覆层。可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。集成在CMOS晶片中的二氧化硅或硅锗可以用作蚀刻停止层。

3. 发明申请

US20100059822A1 METHOD AND SYSTEM FOR MONOLITHIC INTEGRATION OF PHOTONICS AND ELECTRONICS IN CMOS PROCESSES 有权
标题翻译： CMOS工艺中光电子和电子单片集成的方法与系统
公开(公告)号：US20100059822A1
公开(公告)日：2010-03-11
申请号：US12554449
申请日：2009-09-04
申请人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
发明人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H04B10/2575 , H01L21/84 , H01L27/1203 , H04B10/40
摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
摘要翻译：公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的单个CMOS晶片上制造光子和电子器件。利用体CMOS工艺和/或利用SOI CMOS工艺的SOI晶片，可以在绝缘体上半导体（SOI）晶片上制造器件。可以使用双重SOI工艺和/或选择性区域生长工艺来制造不同的厚度。可以利用一个或多个氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。可以利用选择性背面蚀刻来制造包覆层。可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。集成在CMOS晶片中的二氧化硅或硅锗可以用作蚀刻停止层。

4. 发明申请

US20120132993A1 Monolithic Integration Of Photonics And Electronics In CMOS Processes 有权
标题翻译： CMOS工艺中光子学与电子学的一体化
公开(公告)号：US20120132993A1
公开(公告)日：2012-05-31
申请号：US13364909
申请日：2012-02-02
申请人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
发明人： Thierry Pinguet , Steffen Gloeckner , Peter De Dobbelaere , Sherif Abdalla , Daniel Kucharski , Gianlorenzo Masini , Kosei Yokoyama , John Guckenberger , Attila Mekis
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H04B10/2575 , H01L21/84 , H01L27/1203 , H04B10/40
摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.
摘要翻译：公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件，用于光子和电子器件，其结合到每个晶片的至少一部分其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。电子器件可以利用穿硅通孔耦合到光学器件。可以使用选择性区域生长过程来制造不同的厚度。可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。可以利用选择性背面蚀刻来制造包覆层。可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

5. 发明申请

US20070217750A1 Interconnecting (mapping) a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array 有权
标题翻译：将二维光电（OE）器件阵列互连（映射）到一维波导阵列
公开(公告)号：US20070217750A1
公开(公告)日：2007-09-20
申请号：US11374777
申请日：2006-03-14
申请人： Russell Budd , Punit Chiniwalla , John Guckenberger , Jeffrey Kash , Jeremy Schaub , Michael Tan , Jeannine Trewhella , Garry Trott
发明人： Russell Budd , Punit Chiniwalla , John Guckenberger , Jeffrey Kash , Jeremy Schaub , Michael Tan , Jeannine Trewhella , Garry Trott
IPC分类号： G02B6/36 , G02B6/26 , G02B6/12 , G02B6/42
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4214 , G02B6/4246
摘要： For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.
摘要翻译：对于包括电路封装和电路通信技术的集成电路，提供了将二维光电（OE）器件阵列互连或映射到一维波导阵列的方法。还提供了用于将二维光电（OE）器件阵列互连或映射到一维波导阵列的布置。

6. 发明申请

US20050129414A1 Testing of transimpedance amplifiers 有权
标题翻译：跨阻放大器测试
公开(公告)号：US20050129414A1
公开(公告)日：2005-06-16
申请号：US10736424
申请日：2003-12-15
申请人： John Guckenberger , Young Kwark , Jeremy Schaub
发明人： John Guckenberger , Young Kwark , Jeremy Schaub
IPC分类号： H04B10/06 , H04B10/12 , H04B10/158
CPC分类号： H04B10/25
摘要： Testing is performed on an amplifier wafer housing a transimpedance amplifier prior to packaging the transimpedance amplifier with an external photodetector, wherein the transimpedance amplifier includes a small, auxiliary, integrated silicon photodetector provided at the input of the transimpedance, in parallel with external photodetector attachment points. The small auxiliary photodetector does not significantly affect the high speed performance of the transimpedance amplifier. The small auxiliary photodetector is provided to facilitate wafer-level testing at the transimpedance amplifier input. To test the transimpedance amplifier, the transimpedance amplifier is stimulated by optically exciting the small auxiliary photodetector, wherein the small auxiliary photodetector is excited using short wavelength light, whereby advantages such as higher efficiency may be obtained. The testing method includes placing the amplifier wafer in a testing system, probing the power and ground connections on the amplifier wafer, illuminating the small auxiliary photodetector on the amplifier wafer, and detecting the output of the transimpedance amplifier housed on the amplifier wafer. The output of the transimpedance amplifier may detected by probing the supply voltage and detecting the switching currents passing through a bias tee using a spectrum analyzer, using a high gain antenna and a sensitive narrow band receiver, or using a high speed electrical probe.
摘要翻译：在将跨阻抗放大器封装在外部光电检测器之前，在放大器晶片上进行测试，其中跨导放大器包括一个小的辅助集成硅光电检测器，其设置在跨阻抗的输入处，与外部光电检测器连接点。小型辅助光电探测器不会显着影响跨阻放大器的高速性能。提供小型辅助光电探测器以便于跨阻放大器输入端的晶圆级测试。为了测试跨阻抗放大器，通过光学激励小型辅助光电探测器来刺激跨阻放大器，其中使用短波长光来激发小的辅助光电探测器，由此可以获得诸如更高效率的优点。测试方法包括将放大器晶片放置在测试系统中，探测放大器晶片上的电源和接地连接，照射放大器晶片上的小辅助光电检测器，以及检测放大晶片上的跨阻放大器的输出。跨导放大器的输出可以通过使用高增益天线和敏感窄带接收机，或使用高速电探测器，利用频谱分析仪探测电源电压和检测通过偏置三通的开关电流来检测。

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