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1. 发明授权

US07054088B2 Information recording and reproducing apparatus and method, and signal decoding circuit for performing timing recovery 失效
公开(公告)号：US07054088B2
公开(公告)日：2006-05-30
申请号：US10273485
申请日：2002-10-18
申请人： Akihiro Yamazaki , Takao Sugawara , Motomu Takatsu , Masaru Sawada
发明人： Akihiro Yamazaki , Takao Sugawara , Motomu Takatsu , Masaru Sawada
IPC分类号： G11B5/35
CPC分类号： G11B20/10009 , G11B5/09 , G11B20/18
摘要： A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

2. 发明授权

US07515369B2 Information recording and reproducing apparatus and method, and signal decoding circuit for performing timing recovery 失效
标题翻译：信息记录和再现装置和方法以及用于执行定时恢复的信号解码电路
公开(公告)号：US07515369B2
公开(公告)日：2009-04-07
申请号：US11388377
申请日：2006-03-24
申请人： Takao Sugawara , Motomu Takatsu , Masaru Sawada
发明人： Takao Sugawara , Motomu Takatsu , Masaru Sawada
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B5/09 , G11B20/18
摘要： A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.
摘要翻译：定时恢复单元从再现数据的头部区域检测相位偏移和频率偏移，并且最初校正它们。定时恢复单元将已经通过固定时钟将头重放信号离散的数据存储到缓冲器中。相位偏移检测器与将数据写入缓冲器的操作并行地检测与数据头区域的相位偏移。同时，频率偏移检测器与将数据写入缓冲器的操作并行地检测数据头区域的频率偏移。检测到的相位偏移的校正值和检测到的频率偏移的校正值最初被设置为数字PLL。当从缓冲器中读出数据时，在头部区域中执行频率导入和相位导入。

3. 发明申请

US20050099907A1 Training method for recording medium reproduction equalizer and recording medium reproduction apparatus 失效
标题翻译：用于记录媒体再现均衡器和记录介质再现装置的训练方法
公开(公告)号：US20050099907A1
公开(公告)日：2005-05-12
申请号：US10722915
申请日：2003-11-26
申请人： Masaru Sawada , Motomu Takatsu , Takao Sugawara
发明人： Masaru Sawada , Motomu Takatsu , Takao Sugawara
IPC分类号： G11B20/10 , G11B7/00 , H03H17/02 , H03H21/00
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10481
摘要： In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of the FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditional vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer. As the restricting conditional vector, a vector is utilized which is a difference between a subsequent coefficient vector obtained in the same condition immediately subsequent to and an antecedent coefficient vector obtained in the same condition immediately antecedent to a reference coefficient comprising the multiplication coefficient for the equalizer obtained upon calculating the equalizer error.
摘要翻译：在用于优化均衡从记录介质读取的读取信号的FIR均衡器的每个抽头的乘法系数的训练操作中，作为用于更新FIR滤波器的每个抽头的乘法系数的受限系数更新向量，使用向量其通过将垂直于预定的限制条件向量的平面投影到基于FIR均衡器的输出与由其确定的再现输出之间的均衡器误差确定的系数更新向量和每个抽头的每个抽头的延迟输入值而获得 FIR均衡器作为限制条件向量，使用作为在紧随其后的相同条件下获得的后续系数向量与在与包括均衡器的乘法系数的参考系数紧密相关的条件下获得的先前系数向量之间的差的向量在计算均衡器误差时获得。

4. 发明授权

US07286596B2 Training method for recording medium reproduction equalizer and recording medium reproduction apparatus 失效
标题翻译：用于记录媒体再现均衡器和记录介质再现装置的训练方法
公开(公告)号：US07286596B2
公开(公告)日：2007-10-23
申请号：US10722915
申请日：2003-11-26
申请人： Masaru Sawada , Motomu Takatsu , Takao Sugawara
发明人： Masaru Sawada , Motomu Takatsu , Takao Sugawara
IPC分类号： H03H7/30 , H03K5/159
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10481
摘要： In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of an FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditioning vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer. As the restricting conditioning vector, a vector is utilized which is a difference between a subsequent coefficient vector obtained in the same condition immediately subsequent to and an antecedent coefficient vector obtained in the same condition immediately antecedent to a reference coefficient comprising the multiplication coefficient for the equalizer obtained upon calculating the equalizer error.
摘要翻译：在用于优化均衡从记录介质读取的读取信号的FIR均衡器的每个抽头的乘法系数的训练操作中，作为用于更新FIR滤波器的每个抽头的乘法系数的受限系数更新向量，使用向量其通过将垂直于预定的限制调节向量的平面投影到基于FIR均衡器的输出与由其确定的再现输出之间的均衡器误差确定的系数更新向量和每个抽头的每个抽头的延迟输入值而获得 FIR均衡器作为限制调节向量，使用这样的矢量，该矢量是在紧随其后的相同条件下获得的后续系数矢量与在与包括均衡器的乘法系数的参考系数紧邻的相同条件下获得的先前系数矢量之间的差值在计算均衡器误差时获得。

5. 发明申请

US20060181797A1 Information recording and reproducing apparatus and method, and signal decoding circuit for performing timing recovery 失效
公开(公告)号：US20060181797A1
公开(公告)日：2006-08-17
申请号：US11388377
申请日：2006-03-24
申请人： Takao Sugawara , Motomu Takatsu , Masaru Sawada
发明人： Takao Sugawara , Motomu Takatsu , Masaru Sawada
IPC分类号： G11B5/09 , G11B5/035
CPC分类号： G11B20/10009 , G11B5/09 , G11B20/18
摘要： A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

6. 发明授权

US07031090B2 Information recording and reproducing apparatus and method and signal decoding circuit having improved noise processing characteristics 失效
标题翻译：具有改善的噪声处理特性的信息记录和再现装置和方法和信号解码电路
公开(公告)号：US07031090B2
公开(公告)日：2006-04-18
申请号：US10045738
申请日：2001-10-29
申请人： Kazuhito Ichihara , Takao Sugawara , Yuichi Sato , Toshihiko Morita , Motomu Takatsu
发明人： Kazuhito Ichihara , Takao Sugawara , Yuichi Sato , Toshihiko Morita , Motomu Takatsu
IPC分类号： G11B5/035
CPC分类号： G11B20/10009
摘要： In a Maximum A posteriori Probability decoding (MAP decoding), a correlation and a deviation of noises for past and future states which depend on input signal patterns in past N bits and future Q bits are calculated by training by a noise correlation arithmetic operating unit 84 and they are stored. Upon reproduction, in a white noise arithmetic operating unit 91, white noise values for the past and future states in which colored noises are converted into white noises are obtained by using the stored correlation and deviation of the noises. In an input signal arithmetic operating unit 92, an input signal (channel information) Λc(yk|Smk) of the MAP decoding is calculated from the white noise values and the deviation for the past and future states. A likelihood in the MAP decoding is obtained from the input signal.
摘要翻译：在最大后验概率解码（MAP解码）中，依赖于过去N位和未来Q位中的输入信号模式的过去和未来状态的噪声的相关和偏差由噪声相关运算单元84进行训练并存储它们。在再现时，在白噪声运算单元91中，通过使用所存储的噪声的相关性和偏差来获得将彩色噪声转换成白噪声的过去和未来状态的白噪声值。在输入信号算术运算单元92中，MAP解码器的输入信号（信道信息）Lambdac（y k k S k S m S k）由白噪声值和过去和未来状态的偏差计算得出。从输入信号获得MAP解码中的似然。

7. 发明申请

US20070210299A1 Single-photon generating device, single-photon detecting device, and optical quantum gate 有权
标题翻译：单光子发生装置，单光子检测装置和光量子门
公开(公告)号：US20070210299A1
公开(公告)日：2007-09-13
申请号：US11522421
申请日：2006-09-18
申请人： Shinichi Hirose , Motomu Takatsu , Tatsuya Usuki , Yasuhiko Arakawa
发明人： Shinichi Hirose , Motomu Takatsu , Tatsuya Usuki , Yasuhiko Arakawa
IPC分类号： H01L29/06 , H01L29/12
CPC分类号： H01L31/035281 , H01L31/02327 , H01L31/03046 , H01L33/20 , H01S5/0201 , Y02E10/50 , Y10S977/949 , Y10S977/95
摘要： A single-photon generating device is configured to have a solid substrate including abase portion, and a pillar portion which is formed on the surface side of the base portion with a localized level existent in the vicinity of the tip of the base portion. The above pillar portion is formed to have a larger cross section on the base portion side than the cross section on the tip side, so that the light generated from the localized level is reflected on the surface, propagated inside the pillar portion, and output from the back face side of the base portion.
摘要翻译：单光子产生装置被配置为具有包括基部的固体基板，并且在基部的尖端附近存在形成有位于基部的表面侧的柱部。上述柱部形成为在基部侧的截面比前端侧的截面大的截面，使得从局部水平产生的光在表面上反射，在柱部内传播，并从基部的背面侧。

8. 发明授权

US06292586B1 Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus 失效
标题翻译：算术单元，相关运算单元和动态图像压缩装置
公开(公告)号：US06292586B1
公开(公告)日：2001-09-18
申请号：US09236345
申请日：1999-01-25
申请人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
发明人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
IPC分类号： G06K936
CPC分类号： G06F17/15
摘要： In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the “product” in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value |c| of the numerical value c, and a sign operation unit for evaluating a sign “sing (c)” of the numerical value c.
摘要翻译：在适于检测两个功能之间的相对差异的相关运算系统中，简化了操作。这使得可以以小规模的硬件并且以很高的精度执行操作。在相关算术运算中采用运算g * h而不是“乘积”。公开了一种运算单元，其中输入两个数字值a和b，并且对两个数值a和b进行预定的操作处理，从而导出代表运算结果的数值c。算术单元具有用于评估绝对值| c |的绝对值运算单元的数值c的符号“sing（c）”的符号运算单元。

9. 发明授权

US5561306A Hetero-bipolar transistor having a plurality of emitters 失效
标题翻译：具有多个发射极的异质双极晶体管
公开(公告)号：US5561306A
公开(公告)日：1996-10-01
申请号：US295538
申请日：1994-08-25
申请人： Kenichi Imamura , Motomu Takatsu , Toshihiko Mori
发明人： Kenichi Imamura , Motomu Takatsu , Toshihiko Mori
IPC分类号： H01L29/73 , H01L21/331 , H01L29/02 , H01L29/08 , H01L29/205 , H01L29/737 , H01L31/0328 , H01L29/06 , H01L31/0336
CPC分类号： H01L29/0817
摘要： A hetero-bipolar transistor includes a collector layer of a first conductivity type, a base layer of a second conductivity type provided on the collector layer, a first emitter structure of the first conductivity type provided on the base layer, and a second emitter structure of the first conductivity type and provided on the base layer, wherein the first and second emitter structures are doped with respect to the base layer, with a sufficiently high impurity concentration level such that a Zener breakdown occurs at the p-n junction formed between the base layer and the first or second emitters upon application of a reverse bias voltage.
摘要翻译：异双极晶体管包括第一导电类型的集电极层，设置在集电极层上的第二导电类型的基极层，设置在基极层上的第一导电类型的第一发射极结构和第二发射极结构第一导电类型并且设置在基极层上，其中第一和第二发射极结构相对于基极层掺杂，具有足够高的杂质浓度水平，使得在形成在基极层和基极层之间的pn结处发生齐纳击穿施加反向偏置电压时的第一或第二发射极。

10. 发明授权

US5281871A Majority logic circuit 失效
标题翻译：多数逻辑电路
公开(公告)号：US5281871A
公开(公告)日：1994-01-25
申请号：US795472
申请日：1991-11-21
申请人： Toshihiko Mori , Motomu Takatsu
发明人： Toshihiko Mori , Motomu Takatsu
IPC分类号： G06F7/50 , G06F7/501 , H03K19/21 , H03K19/23 , H03K19/013
CPC分类号： G06F7/5013 , H03K19/212 , H03K19/215 , H03K19/23 , G06F2207/4822
摘要： A logic circuit including a transistor having a control electrode connected to three input terminals at which are received three respective input signals, each having, selectively, either a high or a low voltage level, and first and second electrodes, one thereof connected to a first power supply potential and the other thereof connected through a diode having N-type negative differential resistance to a second, lower power supply potential. An output terminal is connected to one of the first and second electrodes of the transistor for deriving an output signal. The load lines of the transistor are set to a first operating point for both a first condition in which all three input signals are at a low voltage level and also a second condition in which two thereof are at a high level and the third is at a low level, and to a second operating point for both a third condition in which only one of the input signals is at the high level and the remaining two input signals are at the low level and also a fourth condition in which all of the three input signals are at the high level. The current conducted by the transistor is at a first level for the first operating point and at a second level, greater than the first level, for the second operating point.
摘要翻译：一种逻辑电路，包括具有连接到三个输入端子的控制电极的晶体管，在三个输入端子处接收三个相应的输入信号，每个输入信号选择性地具有高电压或低电压电平，以及第一和第二电极，其中一个连接到第一电源电位，另一个通过具有N型负差分电阻的二极管连接到第二较低电源电位。输出端子连接到晶体管的第一和第二电极之一，用于导出输出信号。对于其中所有三个输入信号都处于低电压电平的第一状态以及其中两个处于高电平的第二状态，并且第三状态处于高电平的第二状态，晶体管的负载线被设置为第一工作点低电平的第二工作点，对于其中只有一个输入信号处于高电平且剩余的两个输入信号处于低电平的第三状态，以及其中三个输入的全部的第四条件信号处于高位。对于第二工作点，由晶体管传导的电流为第一工作点的第一电平，大于第一电平的第二电平。

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