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1. 发明授权

US07122433B2 Method for manufacturing trench gate semiconductor device 失效
标题翻译：沟槽栅极半导体器件的制造方法
公开(公告)号：US07122433B2
公开(公告)日：2006-10-17
申请号：US10821904
申请日：2004-04-09
申请人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
发明人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/42372 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7811 , H01L2924/13055 , H01L2924/13091 , H01L2924/30105
摘要： A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e). The lateral extent of the conductive layer (11c) terminates in an edge (11a,11b) that is defined on the trench-etch mask (51).
摘要翻译：为蜂窝状沟槽栅极半导体器件（例如功率MOSFET）中的至少一组电池提供器件端接结构和/或栅极汇流条结构和/或其它端部结构。在该端部结构中，例如多晶硅栅极材料的导电层（11c）在中间绝缘层（55）上延伸穿过沟道容纳区域（15）的较高掺杂（P +）端部区域（150））。该绝缘层（55）包括沟槽蚀刻掩模（51）的优选地包括氮化硅的区域（51e），其厚度大于栅极电介质层（17）的厚度。窗口（51a）在端部沟槽（20e）延伸到P +区域（150）的位置处延伸穿过沟槽蚀刻掩模（51）。端部沟槽（20e）是绝缘栅极沟槽（20）延伸到P +区域（150）中并且容纳沟槽栅极（11）的延伸部分（11e）的延伸。导电层（11c）经由窗口（51e）连接到沟槽栅延伸部（11e）。导电层（11c）的横向范围终止于限定在沟槽蚀刻掩模（51）上的边缘（11a，11b）。

2. 发明授权

US06800900B2 Trench-gate semiconductor devices and their manufacture 有权
标题翻译：沟槽门半导体器件及其制造
公开(公告)号：US06800900B2
公开(公告)日：2004-10-05
申请号：US10213460
申请日：2002-08-06
申请人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
发明人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/42372 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7811 , H01L2924/13055 , H01L2924/13091 , H01L2924/30105
摘要： A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e). The lateral extent of the conductive layer (11c) terminates in an edge (11a,11b) that is defined on the trench-etch mask (51).
摘要翻译：为蜂窝状沟槽栅极半导体器件（例如功率MOSFET）中的至少一组电池提供器件端接结构和/或栅极汇流条结构和/或其它端部结构。在该端部结构中，例如多晶硅栅极材料的导电层（11c）在通道容纳区域（15）的较高掺杂（P +）端部区域（150）上的中间绝缘层（55）上延伸，。该绝缘层（55）包括沟槽蚀刻掩模（51）的优选地包括氮化硅的区域（51e），其厚度大于栅极电介质层（17）的厚度。窗口（51a）在端部沟槽（20e）延伸到P +区域（150）的位置处延伸穿过沟槽蚀刻掩模（51）。端部沟槽（20e）是绝缘栅极沟槽（20）延伸到P +区域（150）中并且容纳沟槽栅极（11）的延伸部分（11e）的延伸。导电层（11c）经由窗口（51e）连接到沟槽栅延伸部（11e）。导电层（11c）的横向延伸终止在限定在沟槽蚀刻掩模（51）上的边缘（11a，11b）中。

3. 发明授权

US06660591B2 Trench-gate semiconductor devices having a channel-accommodating region and their methods of manufacture 失效
标题翻译：具有通道容纳区域的沟槽栅半导体器件及其制造方法
公开(公告)号：US06660591B2
公开(公告)日：2003-12-09
申请号：US10134209
申请日：2002-04-26
申请人： Steven T. Peake , Georgios Petkos , Robert J. Farr , Christopher M. Rogers , Raymond J. Grover , Peter J. Forbes
发明人： Steven T. Peake , Georgios Petkos , Robert J. Farr , Christopher M. Rogers , Raymond J. Grover , Peter J. Forbes
IPC分类号： H01L21336
CPC分类号： H01L29/66348 , H01L29/42368
摘要： Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. Thereby, the source region (13) and a contact window (18a) for a source electrode (33) can be self-aligned to a narrow trench (20) containing the trench-gate (11). Thereby, the channel-accommodating region (15) can also be provided after forming the trench-gate (11), and with very good control of its doping concentration (Na; p) adjacent to the trench (20). To achieve this control, its dopant is provided after removing the spacers (52) from the mask (51) so as to form a doping window (51b), which may also be used for the source dopant, adjacent to the trench-gate (11). A high energy dopant implant (61) or other doping process provides this channel dopant adjacent to the trench (20) and extending laterally below the mask (51,51n). A remarkably uniform doping profile can be achieved beneath the doping window (51b) and beneath the mask (51,51n). By using a high ion energy and high dose, the dopant ions (61) at the doping window (51b) can be laterally scattered below the mask (51) while those at the mask (51) penetrate there-through to be implanted in the underlying portion of the body (100).
摘要翻译：紧凑型沟槽栅极半导体器件（例如具有亚微米间距（Yc）的蜂窝功率MOSFET）以具有以不同方式使用侧壁间隔物（52）的自对准技术制造。因此，用于源电极（33）的源区（13）和接触窗（18a）可以与包含沟槽栅极（11）的窄沟槽（20）自对准。由此，也可以在形成沟槽栅极（11）之后提供沟道容纳区域（15），并且非常好地控制与沟槽（20）相邻的掺杂浓度（Na; p）。为了实现该控制，在从掩模（51）去除间隔物（52）之后提供其掺杂剂，以形成邻近沟槽栅极（也可用于源极掺杂剂）的掺杂窗口（51b） 11）。高能量掺杂剂注入（61）或其它掺杂工艺提供了与沟槽（20）相邻并且在掩模（51,51n）下方横向延伸的该沟道掺杂剂。在掺杂窗口（51b）下面和掩模（51,51n）下面可以实现非常均匀的掺杂分布。通过使用高离子能量和高剂量，掺杂窗口（51b）处的掺杂剂离子（61）可以横向散布在掩模（51）下方，而掩模（51）处的掺杂离子（61）穿过其中，以便被植入到身体（100）的下部。

4. 发明授权

US06534367B2 Trench-gate semiconductor devices and their manufacture 有权
公开(公告)号：US06534367B2
公开(公告)日：2003-03-18
申请号：US10134213
申请日：2002-04-26
申请人： Steven T. Peake , Georgios Petkos , Robert J. Farr , Christopher M. Rogers , Raymond J. Grover , Peter J. Forbes
发明人： Steven T. Peake , Georgios Petkos , Robert J. Farr , Christopher M. Rogers , Raymond J. Grover , Peter J. Forbes
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41766 , H01L29/42368 , H01L29/6634 , H01L29/66348 , H01L29/66727 , H01L29/66848
摘要： Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11). Furthermore, implantation of the source region (13) is facilitated, and a channel-accommodating region (15) can also be provided using a high energy implant (61) after providing the insulating overlayer (18).

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