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1. 发明授权

US07107429B2 Data access in a processor 有权
公开(公告)号：US07107429B2
公开(公告)日：2006-09-12
申请号：US11364927
申请日：2006-03-01
申请人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Nel Bailey , David Plowman
发明人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Nel Bailey , David Plowman
IPC分类号： G06F12/00
CPC分类号： G06F9/3013 , G06F9/30098 , G06F9/30141 , G06F9/30149 , G06F9/30167 , G06F9/3885 , G06F15/8053
摘要： A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

2. 发明申请

US20060146060A1 Data access in a processor 有权
标题翻译：处理器中的数据访问
公开(公告)号：US20060146060A1
公开(公告)日：2006-07-06
申请号：US11364927
申请日：2006-03-01
申请人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Nel Bailey , David Plowman
发明人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Nel Bailey , David Plowman
IPC分类号： G06F12/06
CPC分类号： G06F9/3013 , G06F9/30098 , G06F9/30141 , G06F9/30149 , G06F9/30167 , G06F9/3885 , G06F15/8053
摘要： A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.
摘要翻译：一种数据处理器，包括：寄存器存储器，其包括存储器单元的阵列，每个单元可通过指定一对坐标的指令来寻址，该坐标标识阵列中的单元。

3. 发明授权

US07818540B2 Vector processing system 有权
标题翻译：矢量处理系统
公开(公告)号：US07818540B2
公开(公告)日：2010-10-19
申请号：US11437385
申请日：2006-05-19
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/80
CPC分类号： G06F9/30036 , G06F9/3842 , G06F9/3885
摘要： A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
摘要翻译：用于执行向量指令的矢量处理系统，定义多个值对的每个指令，要执行的操作和修改器，所述向量处理系统包括多个并行处理单元，每个并行处理单元被布置为接收所述一对值中的一个，以及何时被选择以实现对所述值对的操作以产生结果，每个处理单元包括至少一个标志，并且可以根据由所述至少一个标志定义的条件来选择，其中所述修饰符定义所述并行处理的条件单位被单独选择。

4. 发明授权

US07028143B2 Narrow/wide cache 有权
公开(公告)号：US07028143B2
公开(公告)日：2006-04-11
申请号：US10413487
申请日：2003-04-15
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F12/02
CPC分类号： G06F9/3828 , G06F9/30145 , G06F9/30167 , G06F9/3885 , G06F9/3889 , G06F12/0804 , G06F12/0888 , Y02D10/13
摘要： A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

5. 发明授权

US08285975B2 Register file with separate registers for compiler code and low level code 有权
标题翻译：使用单独的寄存器为编译器代码和低级代码注册文件
公开(公告)号：US08285975B2
公开(公告)日：2012-10-09
申请号：US10413488
申请日：2003-04-15
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F9/30
CPC分类号： G06F9/30138 , G06F9/30036 , G06F9/30101 , G06F9/30149
摘要： A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.
摘要翻译：一种处理器核心，包括执行单元和寄存器文件，所述寄存器文件包括编译器生成的代码可访问的第一多个寄存器和不能被编译器生成的代码访问的第二多个寄存器，由此所述第二个寄存器的寄存器多个寄存器可被低级代码访问。

6. 发明申请

US20070061550A1 INSTRUCTION EXECUTION IN A PROCESSOR 有权
标题翻译：处理者的指示执行
公开(公告)号：US20070061550A1
公开(公告)日：2007-03-15
申请号：US11556937
申请日：2006-11-06
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/00
CPC分类号： G06F9/30036 , G06F9/30021 , G06F9/3013 , G06F9/30185 , G06F9/3889 , G06F15/8076
摘要： A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.
摘要翻译：一种处理器，包括：标量处理单元，用于执行每个定义单个值对的标量指令; 矢量处理单元，用于执行各自定义多个值对的矢量指令，所述矢量处理单元包括多个值处理单元，每个所述值处理单元可操作以处理所述多个值对之一并产生相应的结果; 以及指令解码器，用于接收包括标量指令和向量指令的单个指令流，并且可操作以将标量指令引导到标量单元，并向矢量单元指示矢量指令。

7. 发明授权

US07457941B2 Vector processing system 有权
标题翻译：矢量处理系统
公开(公告)号：US07457941B2
公开(公告)日：2008-11-25
申请号：US11324494
申请日：2006-01-03
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/80
CPC分类号： G06F15/8092 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F15/8076
摘要： A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.
摘要翻译：一种用于执行向量指令的矢量处理系统，定义多对值的每个指令，对每个所述值对执行的操作和标量修改器，所述向量处理系统包括多个并行处理单元，每个并行处理单元被布置为接收一个并且对所述值对实现所定义的操作以产生相应的结果; 以及标量结果单元，用于接收并行处理单元的结果，并且以由标量修饰符定义的方式使用所述结果以产生用于所述指令的单个输出值。

8. 发明授权

US07350057B2 Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction 有权
标题翻译：矢量/标量系统中的矢量/标量系统中的标量结果生成方法，由向量单位，根据向量指示中的修饰符向量结果
公开(公告)号：US07350057B2
公开(公告)日：2008-03-25
申请号：US11556937
申请日：2006-11-06
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F9/302
CPC分类号： G06F9/30036 , G06F9/30021 , G06F9/3013 , G06F9/30185 , G06F9/3889 , G06F15/8076
摘要： Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.
摘要翻译：这里描述了一种用于执行指令的方法和系统。该系统包括用于执行每个定义单个值对的标量指令的标量单元; 矢量单元，用于执行各自定义多个值对的矢量指令; 以及指令解码器，用于接收包括标量指令和向量指令的单个指令流，并且可操作以将标量指令引导到标量单元，并向矢量单元指示矢量指令。向量单元可以包括多个值处理单元和标量结果单元。标量单元可以包括标量寄存器文件。通过允许向量单元访问标量寄存器文件并允许标量单元访问标量结果单元的输出，可以实现向量单元和标量单元之间的通信。标量结果单元的输出可以基于来自多个值处理单元的输出的相对大小。

9. 发明申请

US20060224865A1 Vector processing system 有权
标题翻译：矢量处理系统
公开(公告)号：US20060224865A1
公开(公告)日：2006-10-05
申请号：US11437385
申请日：2006-05-19
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F9/44
CPC分类号： G06F9/30036 , G06F9/3842 , G06F9/3885
摘要： A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
摘要翻译：用于执行向量指令的矢量处理系统，定义多个值对的每个指令，要执行的操作和修改器，所述向量处理系统包括多个并行处理单元，每个并行处理单元被布置为接收所述一对值中的一个，以及何时被选择以实现对所述值对的操作以产生结果，每个处理单元包括至少一个标志，并且可以根据由所述至少一个标志定义的条件来选择，其中所述修饰符定义所述并行处理的条件单位被单独选择。

10. 发明申请

US20060136700A1 Vector processing system 有权
公开(公告)号：US20060136700A1
公开(公告)日：2006-06-22
申请号：US11324494
申请日：2006-01-03
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/00
CPC分类号： G06F15/8092 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F15/8076
摘要： A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

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