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1. 发明申请

US20050051904A1 Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow 有权
公开(公告)号：US20050051904A1
公开(公告)日：2005-03-10
申请号：US10745059
申请日：2003-12-22
申请人： Sarah Kim , Kevin Lee , Steven Towle , Anna George
发明人： Sarah Kim , Kevin Lee , Steven Towle , Anna George
IPC分类号： H01L21/60 , H01L21/768 , H01L23/36 , H01L23/485 , H01L23/498 , H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L24/12 , H01L21/76838 , H01L23/36 , H01L23/49816 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L24/11 , H01L24/16 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/05666 , H01L2224/13099 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014
摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.

2. 发明申请

US20060012039A1 Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow 审中-公开
标题翻译：使用喷涂或层压处理C4晶圆级厚金属集成流的厚ILD层的方法
公开(公告)号：US20060012039A1
公开(公告)日：2006-01-19
申请号：US11221453
申请日：2005-09-07
申请人： Sarah Kim , Kevin Lee , Steven Towle , Anna George
发明人： Sarah Kim , Kevin Lee , Steven Towle , Anna George
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L24/81 , H01L21/31051 , H01L21/76801 , H01L21/76829 , H01L21/76838 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/1147 , H01L2224/13099 , H01L2224/13111 , H01L2224/73253 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01061 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
摘要翻译：在芯片或晶片级别的受控崩溃芯片连接（C4）凸起处形成具有一个或多个厚金属层的互连结构的工艺流程。互连结构可以用在微处理器的后端互连中。工艺流程可以包括在具有高纵横比结构的表面上形成具有喷涂或层压的层间电介质。

3. 发明申请

US20070190776A1 Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow 审中-公开
标题翻译：使用喷涂或层压处理C4晶圆级厚金属集成流的厚ILD层的方法
公开(公告)号：US20070190776A1
公开(公告)日：2007-08-16
申请号：US11740246
申请日：2007-04-25
申请人： Sarah Kim , Kevin Lee , Steven Towle , Anna George
发明人： Sarah Kim , Kevin Lee , Steven Towle , Anna George
IPC分类号： H01L21/4763
CPC分类号： H01L24/81 , H01L21/31051 , H01L21/76801 , H01L21/76829 , H01L21/76838 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/1147 , H01L2224/13099 , H01L2224/13111 , H01L2224/73253 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01061 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
摘要翻译：在芯片或晶片级别的受控崩溃芯片连接（C4）凸起处形成具有一个或多个厚金属层的互连结构的工艺流程。互连结构可以用在微处理器的后端互连中。工艺流程可以包括在具有高纵横比结构的表面上形成具有喷涂或层压的层间电介质。

4. 发明申请

US20050051894A1 Thick metal layer integrated process flow to improve power delivery and mechanical buffering 失效
公开(公告)号：US20050051894A1
公开(公告)日：2005-03-10
申请号：US10659044
申请日：2003-09-09
申请人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
发明人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
IPC分类号： H01L21/60 , H01L21/768 , H01L23/36 , H01L23/485 , H01L23/498 , H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L24/12 , H01L21/76838 , H01L23/36 , H01L23/49816 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L24/11 , H01L24/16 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/05666 , H01L2224/13099 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014
摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

5. 发明申请

US20060076678A1 Thick metal layer integrated process flow to improve power delivery and mechanical buffering 审中-公开
标题翻译：厚金属层集成工艺流程，以改善动力传递和机械缓冲
公开(公告)号：US20060076678A1
公开(公告)日：2006-04-13
申请号：US11281709
申请日：2005-11-16
申请人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
发明人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L21/76838 , H01L23/36 , H01L23/49816 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L24/11 , H01L24/16 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/05666 , H01L2224/13099 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014
摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
摘要翻译：在芯片或晶片级的受控崩溃芯片连接（C 4）凸起处制造具有一个或多个厚金属层的互连结构的工艺流程。互连结构可以用在微处理器的后端互连中。一个或多个集成的厚金属层可以改善功率传递并且降低在管芯/封装接口处的管芯的机械应力。

6. 发明申请

US20060051021A1 Waveguide coupling mechanism 有权
公开(公告)号：US20060051021A1
公开(公告)日：2006-03-09
申请号：US10934858
申请日：2004-09-03
申请人： Henning Braunisch , Steven Towle , Daoqiang Lu , Gilroy Vandentop , Anna George
发明人： Henning Braunisch , Steven Towle , Daoqiang Lu , Gilroy Vandentop , Anna George
IPC分类号： G02B6/32
CPC分类号： G02B6/30 , G02B6/32
摘要： A system is disclosed. The system includes an external waveguide and an IC coupled to the external waveguide. The IC includes at least two lenses and a second waveguide. The lenses couple radiant energy from the external waveguide to the second waveguide.

7. 发明申请

US20050136640A1 Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same 审中-公开
标题翻译：显示与安装在其上的基板相当的有效热膨胀系数的模具及其制造方法
公开(公告)号：US20050136640A1
公开(公告)日：2005-06-23
申请号：US10956621
申请日：2004-09-30
申请人： Chuan Hu , Steven Towle , Anna George
发明人： Chuan Hu , Steven Towle , Anna George
IPC分类号： H01L23/14 , H01L23/367 , H01L21/44
CPC分类号： H01L23/49568 , H01L23/142 , H01L23/367 , H01L23/373 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04026 , H01L2224/16225 , H01L2224/16227 , H01L2224/29101 , H01L2224/29144 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2224/48472 , H01L2224/73253 , H01L2224/73265 , H01L2224/82039 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A thinned die is disposed on a heat sink and bonded by a thermal interface material (TIM) that includes a gold-tin solder. The thinned die exhibits a die-effective coefficient of thermal expansion (CTE) that substantially matches the CTE of the heat sink. A process of bonding the die includes thermal bonding. A process of bonding the thinned die to a heat sink before bonding the die to an electrical interposer. A computing system includes a semconductive die that is gold-tin bonded to the heat sink, and it is coupled to at least one input-output device.
摘要翻译：减薄的模具设置在散热器上并且通过包含金锡焊料的热界面材料（TIM）结合。薄型模具表现出与散热器的CTE基本相匹配的有效的热膨胀系数（CTE）。模具的结合工艺包括热粘合。在将模具粘合到电插入器之前，将薄模具粘合到散热器上的过程。一种计算系统包括一金属锡结合到该散热器上的导电管芯，并且该导电管芯耦合至少一个输入输出装置。

8. 发明申请

US20050070087A1 Wafer-level thick film standing-wave clocking 失效
公开(公告)号：US20050070087A1
公开(公告)日：2005-03-31
申请号：US10676958
申请日：2003-09-30
申请人： Henning Braunisch , Steven Towle , Anna George
发明人： Henning Braunisch , Steven Towle , Anna George
IPC分类号： H01L21/4763 , H01L23/48 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5226 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to the clock source. The metal layer is embedded in dielectric layers made of thick film using a wafer-level thick film (WLTF) process.

9. 发明授权

US07888183B2 Thinned die integrated circuit package 有权
标题翻译：薄模集成电路封装
公开(公告)号：US07888183B2
公开(公告)日：2011-02-15
申请号：US12042392
申请日：2008-03-05
申请人： Cheng-Yi Liu , Johanna Swan , Steven Towle , Anna George, legal representative , Chuan Hu
发明人： Cheng-Yi Liu , Johanna Swan , Steven Towle , Chuan Hu
IPC分类号： H01L21/44
CPC分类号： H01L24/97 , H01L21/4871 , H01L23/142 , H01L23/36 , H01L23/367 , H01L23/49816 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L2224/0401 , H01L2224/04026 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/13099 , H01L2224/16225 , H01L2224/16227 , H01L2224/20 , H01L2224/211 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/82039 , H01L2224/92244 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.
摘要翻译：一种方法和装置提供具有改进的散热和更容易制造的集成电路封装。集成电路封装包括使用导热材料附着到散热器的薄化半导体管芯。减薄的模头降低了模具/散热器组合的热阻，以改善从模具的热提取以及消除制造中的加工步骤。此外，薄型模具变得更加柔顺，因为它承受散热器的热/机械性能，以减少模具的应力引起的开裂。

10. 发明申请

US20050127528A1 Underfill integration for optical packages 有权
标题翻译：光学封装的底部填充集成
公开(公告)号：US20050127528A1
公开(公告)日：2005-06-16
申请号：US11036302
申请日：2005-01-14
申请人： Daoqiang Lu , Steven Towle , Anna George
发明人： Daoqiang Lu , Steven Towle , Anna George
IPC分类号： G02B6/42 , H01L21/44 , H01L21/56 , H01L29/40
CPC分类号： G02B6/4214 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/00014 , H01L2924/00 , H01L2224/0401
摘要： The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material. Also disclosed is a process comprising flip-chip bonding an optical die to a substrate, the optical die including at least one optically active area on a surface thereof facing the substrate, dispensing an optically transparent material between the optical die and the substrate, wherein the optically transparent material covers the at least one optically active area, dispensing an underfill material in the volume between the optical die and the substrate not occupied by the optically transparent material, and curing the optically transparent material and the underfill material. Other embodiments are described and claimed.
摘要翻译：本申请公开了一种装置，其包括结合到基板并限定光学管芯和基板之间的体积的光学晶片倒装芯片，光学管芯包括在面向基板的管芯的表面上的光学有效区域，光学透明材料占据至少基本对应于光学活性区域的那些部分，以及占据未被光学透明材料占据的部分体积的底部填充材料。还公开了一种包括将光学裸片倒装芯片结合到衬底的工艺，该光学裸片在其面向衬底的表面上包括至少一个光学活性区域，在光学裸片和衬底之间分配光学透明材料，其中，光学透明材料覆盖至少一个光学活性区域，在光学裸片和未被光学透明材料占据的基底之间的体积中分配底部填充材料，并固化光学透明材料和底部填充材料。描述和要求保护其他实施例。

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