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1. 发明授权

US09875805B2 Double lockout in non-volatile memory 有权
公开(公告)号：US09875805B2
公开(公告)日：2018-01-23
申请号：US14928860
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Huai-Yuan Tseng , Deepanshu Dutta
IPC分类号： G11C16/34 , G11C16/10 , G11C11/56 , G11C16/32
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/32 , G11C2211/5621
摘要： A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.

2. 发明授权

US09852800B2 Adaptive determination of program parameter using program of erase rate 有权
公开(公告)号：US09852800B2
公开(公告)日：2017-12-26
申请号：US15062661
申请日：2016-03-07
申请人： SanDisk Technologies Inc.
发明人： Murong Lang , Deepanshu Dutta , Cynthia Hsu
IPC分类号： G11C16/16 , G11C16/34 , G11C16/26
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/3445 , G11C16/3459
摘要： Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.

3. 发明授权

US09721672B1 Multi-die programming with die-jumping induced periodic delays 有权
公开(公告)号：US09721672B1
公开(公告)日：2017-08-01
申请号：US15099781
申请日：2016-04-15
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Arash Hazeghi , Huai-Yuan Tseng , Cynthia Hsu , Navneeth Kankani
IPC分类号： G11C16/32 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C7/04 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

4. 发明授权

US09704595B1 Self-detecting a heating event to non-volatile storage 有权
公开(公告)号：US09704595B1
公开(公告)日：2017-07-11
申请号：US15087242
申请日：2016-03-31
申请人： SanDisk Technologies Inc.
发明人： Alon Eyal , Idan Alrod , Eran Sharon , Ishai Ilani , Mark Murin , David Rozman , Wei-Cheng Lien , Deepanshu Dutta , Changyuan Chen
IPC分类号： G11C13/00 , G11C16/34 , G11C16/14
CPC分类号： G11C16/3431 , G11C7/04 , G11C7/1045 , G11C11/5628 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C16/0483 , G11C16/10 , G11C16/14
摘要： Techniques are provided for non-volatile storage self-detecting that a heating event has occurred to the non-volatile storage. One example of the heating event is an Infrared (IR) reflow process. In one aspect, a block of memory cells in a memory device are put through a number of program/erase cycles. A group of the memory cells in the cycled block are programmed to a reference threshold voltage distribution. Some time may pass after programming the cycled block. The memory device self-detects that there has been a heating event in response to a shift in the reference VT distribution being more than an allowed amount. The memory device may switch from a first programming mode to a second programming mode in response to detecting that the heating event has occurred.

5. 发明申请

US20170125101A1 PROGRAM SEQUENCING 有权
公开(公告)号：US20170125101A1
公开(公告)日：2017-05-04
申请号：US15061940
申请日：2016-03-04
申请人： SanDisk Technologies, Inc.
发明人： Xiaochang Miao , Ken Oowada , Genki Sano , Deepanshu Dutta
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C2211/5648
摘要： Apparatuses, systems, methods, and computer program products are disclosed for program sequencing. An apparatus includes a block of non-volatile storage cells having a plurality of word lines. The word lines are organized into a monotonically increasing sequence. The apparatus includes a controller for the block. The controller is configured to program a set of storage cells of a word line to one or more storage states above a predetermined threshold and to program a set of storage cells of a previous word line adjacent to and before the word line in the sequence, to one or more storage states below the predetermined threshold after programming the set or storage cells of the word line to the one or more storage states above the predetermined threshold.

6. 发明申请

US20170084328A1 WRITE ABORT DETECTION FOR MULTI-STATE MEMORIES 有权
公开(公告)号：US20170084328A1
公开(公告)日：2017-03-23
申请号：US14860086
申请日：2015-09-21
申请人： SanDisk Technologies Inc.
发明人： Cynthia Hua-Ling Hsu , Aaron Lee , Abhijeet Manohar , Deepanshu Dutta
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3459
摘要： Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

7. 发明申请

US20160314844A1 NATURAL THRESHOLD VOLTAGE COMPACTION WITH DUAL PULSE PROGRAM FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的双脉冲程序的自然阈值电压
公开(公告)号：US20160314844A1
公开(公告)日：2016-10-27
申请号：US14926167
申请日：2015-10-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Huai-Yuan Tseng , Farookh Moogat
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C8/12 , G11C11/5628 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of memory cells based on programming performance. Based on the classifying, the control circuit applies different programming signals to different subsets of the memory cells being programmed to a common data state.
摘要翻译：与非易失性存储器单元通信的控制电路被配置为基于编程性能将存储器单元区分和分类成不同的存储器单元子集。基于分类，控制电路将不同的编程信号应用于被编程为公共数据状态的存储器单元的不同子集。

8. 发明申请

US20160300620A1 MULTIPLE BIT LINE VOLTAGE SENSING FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的多位线电压感测
公开(公告)号：US20160300620A1
公开(公告)日：2016-10-13
申请号：US14817767
申请日：2015-08-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Huai-Yuan Tseng , Dana Lee , Ken Oowada , Shih-Chung Lee
IPC分类号： G11C16/34 , G11C16/28 , G11C16/10 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/3459 , G11C2211/5624 , G11C2211/5631 , G11C2211/5632
摘要： A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the memory cells. While applying the reference voltage to the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.
摘要翻译：非易失性存储器系统包括以三维结构排列的多个存储器单元和与存储器单元通信的一个或多个控制电路。一个或多个控制电路被配置为对存储器单元编程和验证编程。一个或多个控制电路被配置为将参考电压施加到存储器单元。在将参考电压施加到多个存储单元的同时，一个或多个控制电路被配置为通过将不同的位线电压施加到连接到多个存储单元的不同位线来检测多个存储单元的不同存储单元是否处于不同的数据状态不同的记忆体。

9. 发明授权

US09449700B2 Boundary word line search and open block read methods with reduced read disturb 有权
标题翻译：边界字线搜索和开放块读取方法，减少读取干扰
公开(公告)号：US09449700B2
公开(公告)日：2016-09-20
申请号：US14621662
申请日：2015-02-13
申请人： SanDisk Technologies Inc.
发明人： Grishma Shah , Deepanshu Dutta
IPC分类号： G11C16/26 , G11C16/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C16/3459
摘要： Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.
摘要翻译：呈现技术以减少部分写入的NAND型非易失性存储器块的读取干扰量，这两者都用于在确定块中的最后写入字线时以及包括写入后验证读取的读取操作。通常使用未被写入的未选择字线以较低的读通电压进行偏置。块的最后写入字线的确定可以在粗细搜索中完成，其中字线被划分成多个区以找到具有最后写入字线的区，其又被分分割为了更精细的搜索。

10. 发明申请

US20160217869A1 Double lockout in non-volatile memory 有权
标题翻译：在非易失性存储器中双重锁定
公开(公告)号：US20160217869A1
公开(公告)日：2016-07-28
申请号：US14928860
申请日：2015-10-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： Huai-Yuan Tseng , Deepanshu Dutta
IPC分类号： G11C16/34 , G11C16/28 , G11C16/10
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/32 , G11C2211/5621
摘要： A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.
摘要翻译：提供了双重锁定编程技术，其具有编程和验证之间的隐藏延迟。提供临时锁定阶段和永久锁定阶段，用于双重锁定编程。临时锁定阶段在永久锁定阶段之前，并用于初始确定何时第一次锁存一个或多个编程脉冲的存储单元。当存储器单元最初通过验证以达到其目标状态时，它暂时被锁定用于针对一个或多个编程脉冲的编程。存储器单元进入永久锁定阶段，在该阶段再次验证其目标状态。当存储器单元第二次通过验证时，在当前程序阶段期间，它被永久锁定用于编程。可以在永久锁定阶段中以一个或多个减少的编程速率对存储器单元进行编程。

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