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1. 发明授权

US09564231B2 Non-volatile memory device and corresponding operating method with stress reduction 有权
标题翻译：非易失性存储器件及相应的减压操作方法
公开(公告)号：US09564231B2
公开(公告)日：2017-02-07
申请号：US14970732
申请日：2015-12-16
申请人： STMICROELECTRONICS S.R.L.
发明人： Francesca Grande , Alfredo Signorello , SantiNunzioAntonino Pagano , Maria Giaquinta
IPC分类号： G11C8/08 , G11C16/14 , G11C16/08
CPC分类号： G11C16/14 , G11C8/08 , G11C8/10 , G11C16/08 , G11C16/16
摘要： A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a control-gate region. The control-gate regions of the memory cells of a same row are coupled to a control-gate terminal and biased at a respective control-gate voltage. A control-gate decoder selects and biases the control-gate regions of the rows at respective control voltages according to operations to be performed on the memory cells. The current-conduction regions of the memory cells are arranged within a same bulk well, and the control-gate decoder has a number of driver blocks each of which supplies the control-gate voltages to a respective number of rows of the array. The driver blocks are provided in respective biasing wells, separate and distinct from one another.
摘要翻译：非易失性存储器件包括具有以行和列排列的存储器单元的存储器阵列。每个单元具有各自的导电区域和控制栅极区域。同一行的存储单元的控制栅极区域耦合到控制栅极端子并且以相应的控制栅极电压偏置。控制栅解码器根据对存储器单元执行的操作，在各个控制电压下选择并偏置行的控制栅极区域。存储器单元的导通区域被布置在相同的体积阱中，并且控制栅极解码器具有多个驱动器块，每个驱动器块将控制栅极电压提供给阵列的相应数量的行。驱动器块设置在各自的偏置井中，彼此分开且不同。

2. 发明授权

US09502115B2 Amplifier stage 有权
标题翻译：放大器级
公开(公告)号：US09502115B2
公开(公告)日：2016-11-22
申请号：US14640236
申请日：2015-03-06
申请人： STMICROELECTRONICS S.R.L.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： H03F3/04 , G11C16/04 , G11C16/12 , H03F1/08 , H03F1/14 , H03F3/45 , G11C16/10 , G11C16/26 , H03F1/02 , H03F3/16 , H03K3/012 , H03K3/353 , G11C29/02
CPC分类号： G11C16/0408 , G11C16/10 , G11C16/12 , G11C16/26 , G11C29/021 , G11C29/028 , H03F1/0205 , H03F1/086 , H03F1/14 , H03F3/16 , H03F3/45183 , H03F3/45475 , H03F2200/129 , H03F2200/153 , H03F2200/45 , H03F2200/516 , H03F2203/45138 , H03F2203/45364 , H03F2203/45511 , H03F2203/45512 , H03K3/012 , H03K3/353
摘要： An input signal is amplified into an output signal that is to be applied to an electrical load including a capacitive component. An amplifier stage includes a pre-amplifier module to receive a first supply voltage, and an output module to receive a second supply voltage. The pre-amplifier module includes a first gain block to pre-amplify the input signal into a first pre-amplified signal, and a second gain block to pre-amplify the input signal into a second pre-amplified signal. A feedback block feeds back the output signal as a feedback signal. A combination element combines the first pre-amplified signal and the feedback signal into a combined signal. The output module combines the combined signal and the second pre-amplified signal into the output signal.
摘要翻译：输入信号被放大为要施加到包括电容分量的电负载的输出信号。放大器级包括用于接收第一电源电压的前置放大器模块和用于接收第二电源电压的输出模块。前置放大器模块包括用于将输入信号预放大成第一预放大信号的第一增益模块和将输入信号预放大成第二预放大信号的第二增益模块。反馈块反馈输出信号作为反馈信号。组合元件将第一预放大信号和反馈信号组合成组合信号。输出模块将组合信号和第二预放大信号组合成输出信号。

3. 发明申请

US20160351264A1 NON-VOLATILE MEMORY DEVICE AND CORRESPONDING OPERATING METHOD WITH STRESS REDUCTION 有权
标题翻译：非易失性存储器件和减少应力的相应操作方法
公开(公告)号：US20160351264A1
公开(公告)日：2016-12-01
申请号：US14970732
申请日：2015-12-16
申请人： STMICROELECTRONICS S.R.L.
发明人： Francesca GRANDE , Alfredo Signorello , SantiNunzioAntonino Pagano , Maria Giaquinta
IPC分类号： G11C16/14 , G11C16/08
CPC分类号： G11C16/14 , G11C8/08 , G11C8/10 , G11C16/08 , G11C16/16
摘要： A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a control-gate region. The control-gate regions of the memory cells of a same row are coupled to a control-gate terminal and biased at a respective control-gate voltage. A control-gate decoder selects and biases the control-gate regions of the rows at respective control voltages according to operations to be performed on the memory cells. The current-conduction regions of the memory cells are arranged within a same bulk well, and the control-gate decoder has a number of driver blocks each of which supplies the control-gate voltages to a respective number of rows of the array. The driver blocks are provided in respective biasing wells, separate and distinct from one another.
摘要翻译：非易失性存储器件包括具有以行和列排列的存储器单元的存储器阵列。每个单元具有各自的导电区域和控制栅极区域。同一行的存储单元的控制栅极区域耦合到控制栅极端子并且以相应的控制栅极电压偏置。控制栅解码器根据对存储器单元执行的操作，在各个控制电压下选择并偏置行的控制栅极区域。存储器单元的导通区域被布置在相同的体积阱中，并且控制栅极解码器具有多个驱动器块，每个驱动器块将控制栅极电压提供给阵列的相应数量的行。驱动器块设置在各自的偏置井中，彼此分开且不同。

4. 发明授权

US09413380B2 High performance digital to analog converter 有权
标题翻译：高性能数模转换器
公开(公告)号：US09413380B2
公开(公告)日：2016-08-09
申请号：US14638246
申请日：2015-03-04
申请人： STMICROELECTRONICS S.r.l.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： G11C16/04 , H03M1/66 , H03F1/34 , H03F3/347 , H03F3/45 , G11C16/06
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.
摘要翻译：数模转换器（DAC）可以包括提供第一模拟值的转换块。 DAC还可以包括用于接收第一模拟值并提供由放大因子放大的第二模拟值的放大块。放大块可以包括用于接收第一模拟值的第一输入端，第二输入端和用于提供第二模拟值的输出端。放大块还可以包括第一电容元件和第二电容元件。第一和第二电容元件可以确定放大系数。放大块还可以包括用于在第二电容元件的第一端子处恢复电荷的控制单元，并且基于该第二模拟值。

5. 发明授权

US08947906B2 High-efficiency driving stage for phase change non-volatile memory devices 有权
标题翻译：用于相变非易失性存储器件的高效率驱动级
公开(公告)号：US08947906B2
公开(公告)日：2015-02-03
申请号：US13771663
申请日：2013-02-20
申请人： STMicroelectronics S.r.l.
发明人： Antonio Conte , Maria Giaquinta , Loredana Chiaramonte
IPC分类号： G11C11/00 , G11C13/00 , G11C5/14
CPC分类号： G11C13/0004 , G11C5/145 , G11C5/147 , G11C13/0038 , G11C13/0069
摘要： A driving stage for a phase change non-volatile memory device may have an output driving unit which supplies an output driving current during an operation of programming of at least one memory cell. A driving-control unit receives an input current and generates at output a first control signal that controls supply of the output driving current by the output driving unit in such a way that a value of this current has a desired relation with the input current. A level-shifter element, set between the output of the driving-control unit and a control input of the output driving unit, determines a level shift of the voltage of the first control signal so as to supply to the control input of the output driving unit a second control signal, having a voltage value that is increased with respect to, and is a function of, the first control signal.
摘要翻译：用于相变非易失性存储器件的驱动级可以具有输出驱动单元，其在至少一个存储器单元的编程操作期间提供输出驱动电流。驱动控制单元接收输入电流并在输出端产生控制由输出驱动单元输出驱动电流的供给的第一控制信号，使得该电流的值与输入电流具有期望的关系。设置在驱动控制单元的输出和输出驱动单元的控制输入之间的电平移动元件确定第一控制信号的电压的电平偏移，以便提供给输出驱动的控制输入单元具有第二控制信号，具有相对于第一控制信号而增加并且是第一控制信号的函数的电压值。

6. 发明公开

US20230318450A1 A VOLTAGE REGULATOR DEVICE, CORRESPONDING METHOD AND DATA STORAGE SYSTEM 审中-公开
公开(公告)号：US20230318450A1
公开(公告)日：2023-10-05
申请号：US18187831
申请日：2023-03-22
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
发明人： Francesca Grande , Francesco La Rosa , Maria Giaquinta , Alfredo Signorello
IPC分类号： H02M3/07 , H02M1/08 , G11C16/30
CPC分类号： H02M3/077 , H02M1/08 , G11C16/30 , G11C16/10
摘要： In an embodiment a device includes a supply node configured to receive a supply voltage, an output node configured to provide an output voltage, a plurality of switching stages coupled to the supply node and to the output node, a sensing circuit coupled to the supply node and configured to provide at least one sensing signal based on the supply voltage and a driver circuit coupled to the sensing circuit and to the plurality of switching stages, wherein the driver circuit is configured to provide the drive signal based on at least one sensing signal exceeding or failing to exceed at least one reference voltage level and to selectively bypass a selected number of the plurality of switching stages based on the drive signal thereby varying an output voltage level at the output node.

7. 发明授权

US09728261B2 High performance digital to analog converter 有权
公开(公告)号：US09728261B2
公开(公告)日：2017-08-08
申请号：US15448813
申请日：2017-03-03
申请人： STMicroelectronics S.r.l.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： G11C16/04 , G11C16/06 , H03M1/66 , H03F3/45
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

8. 发明申请

US20170178731A1 HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER 审中-公开
公开(公告)号：US20170178731A1
公开(公告)日：2017-06-22
申请号：US15448813
申请日：2017-03-03
申请人： STMicroelectronics S.r.l.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： G11C16/06 , H03F3/45 , H03M1/66
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

9. 发明授权

US09640261B2 High performance digital to analog converter 有权
公开(公告)号：US09640261B2
公开(公告)日：2017-05-02
申请号：US15198161
申请日：2016-06-30
申请人： STMICROELECTRONICS S.R.L.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： G11C16/04 , G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03M1/66
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

10. 发明申请

US20150263758A1 HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER 有权
标题翻译：高性能数字到模拟转换器
公开(公告)号：US20150263758A1
公开(公告)日：2015-09-17
申请号：US14638246
申请日：2015-03-04
申请人： STMICROELECTRONICS S.r.l.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： H03M1/66 , G11C16/06
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.
摘要翻译：数模转换器（DAC）可以包括提供第一模拟值的转换块。 DAC还可以包括用于接收第一模拟值并提供由放大因子放大的第二模拟值的放大块。放大块可以包括用于接收第一模拟值的第一输入端，第二输入端和用于提供第二模拟值的输出端。放大块还可以包括第一电容元件和第二电容元件。第一和第二电容元件可以确定放大系数。放大块还可以包括用于在第二电容元件的第一端子处恢复电荷的控制单元，并且基于该第二模拟值。

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