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1. 发明授权

US11742040B2 Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory 有权
公开(公告)号：US11742040B2
公开(公告)日：2023-08-29
申请号：US17704345
申请日：2022-03-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/10 , G11C16/06 , G11C29/02 , G11C5/06 , G11C16/26 , G11C16/10
CPC分类号： G11C29/025 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C16/06 , G11C16/102 , G11C16/26 , G11C29/022 , G11C29/028
摘要： A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

2. 发明授权

US09653132B2 Semiconductor packages usable with semiconductor chips having different pad arrangements and electronic devices having the same 有权
公开(公告)号：US09653132B2
公开(公告)日：2017-05-16
申请号：US15051896
申请日：2016-02-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dae-Hoon Na , Hyun-Jin Kim , Jeong-Don Ihm
IPC分类号： G11C8/12 , G11C16/08 , H01L23/00 , H01L25/065 , G11C16/10 , H01L23/525 , G11C5/06 , G11C16/26 , G11C5/04 , G11C5/02
CPC分类号： G11C8/12 , G11C5/02 , G11C5/04 , G11C5/063 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/022 , G11C29/48 , G11C2029/4402 , H01L23/50 , H01L23/5256 , H01L24/06 , H01L24/48 , H01L25/0657 , H01L2224/48137 , H01L2224/48177 , H01L2225/06506 , H01L2924/00014 , H01L2924/1438 , H01L2224/45099
摘要： A semiconductor package includes an external electrode, an interface chip, and a semiconductor chip. The interface chip includes an external interface pad bonded to the external electrode, a plurality of internal interface pads, and an interface circuit coupled between the external interface pad and the plurality of internal interface pads. The semiconductor chip includes a signal pad that is selectively bonded to one of the plurality of internal interface pads. The interface circuit activates a connection between a selected pad, which corresponds to a pad that is bonded to the signal pad among the plurality of internal interface pads, and the external interface pad, and deactivates connections between unselected pads, which correspond to pads that are not bonded to the signal pad among the plurality of internal interface pads, and the external interface pad.

3. 发明申请

US20170060164A1 REGULATOR CIRCUIT AND POWER SYSTEM INCLUDING THE SAME 有权
标题翻译：包括它的调节器电路和电源系统
公开(公告)号：US20170060164A1
公开(公告)日：2017-03-02
申请号：US15224927
申请日：2016-08-01
申请人： Samsung Electronics Co., Ltd.
发明人： Jeong-Don Ihm , Siddharth Katare
IPC分类号： G05F3/26
CPC分类号： G05F3/262
摘要： A regulator circuit includes a power transistor, a current minor, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current minor provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.
摘要翻译：调节器电路包括功率晶体管，电流辅助电极，第一NMOS晶体管，第二NMOS晶体管和电流源。功率晶体管具有连接到外部电源电压源的源极，连接到具有连接到输出内部电源电压的第二节点的第一电压和漏极的第一节点的栅极。当前小电流向具有第二电压的第三节点提供第一电流，并向第一节点提供第二电流。第一NMOS晶体管具有连接到第一节点的漏极，接收第一参考电压的栅极和连接到第四节点的源极。第二NMOS晶体管具有连接到第三节点的漏极，连接到第二节点的栅极和连接到第四节点的源极。

4. 发明授权

US09461656B2 Injection-locked phase locked loop circuits using delay locked loops 有权
标题翻译：使用延迟锁定环的注入锁相环路电路
公开(公告)号：US09461656B2
公开(公告)日：2016-10-04
申请号：US14558072
申请日：2014-12-02
申请人： Samsung Electronics Co., Ltd.
发明人： Hye-Yoon Joo , Seung-Jun Bae , Young-Soo Sohn , Ho-Sung Song , Jeong-Don Ihm
IPC分类号： H03L7/06 , H03L7/087 , H03L7/07 , H03L7/083 , H03L7/099 , G11C7/22
CPC分类号： H03L7/087 , G11C7/222 , H03L7/07 , H03L7/083 , H03L7/0995
摘要： An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.
摘要翻译：注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。将DLL时钟作为VCO的注入时钟注入到VCO中。

5. 发明授权

US11705166B2 Memory device including on-die-termination circuit 有权
公开(公告)号：US11705166B2
公开(公告)日：2023-07-18
申请号：US17182357
申请日：2021-02-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C2207/105
摘要： A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

6. 发明授权

US10672436B2 Memory device including on-die-termination circuit 审中-公开
公开(公告)号：US10672436B2
公开(公告)日：2020-06-02
申请号：US16058709
申请日：2018-08-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/10
摘要： A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

7. 发明申请

US20200091021A1 DEFECT DETECTION STRUCTURE OF A SEMICONDUCTOR DIE, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD OF DETECTING DEFECTS IN SEMICONDUCTOR DIE 审中-公开
公开(公告)号：US20200091021A1
公开(公告)日：2020-03-19
申请号：US16357674
申请日：2019-03-19
申请人： Samsung Electronics Co., Ltd.
发明人： Min-Jae Lee , Sang-Lok Kim , Byung-Hoon Jeong , Tae-Sung Lee , Jeong-Don Ihm , Jae-Yong Jeong , Young-Don Choi
IPC分类号： H01L21/66 , H01L23/528
摘要： A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

8. 发明授权

US10559373B2 Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory 有权
公开(公告)号：US10559373B2
公开(公告)日：2020-02-11
申请号：US16458933
申请日：2019-07-01
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/10 , G11C29/02 , G11C5/06 , G11C16/26 , G11C16/10 , G11C16/06
摘要： A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

9. 发明授权

US10291275B2 Reception interface circuits supporting multiple communication standards and memory systems including the same 有权
公开(公告)号：US10291275B2
公开(公告)日：2019-05-14
申请号：US15397012
申请日：2017-01-03
申请人： Samsung Electronics Co., Ltd.
发明人： Seon-Kyoo Lee , Byung-Hoon Jeong , Jeong-Don Ihm , Young-Don Choi
IPC分类号： H03F1/32 , H03F1/34 , H04B1/24 , H04L25/03 , H04L12/863 , H04L25/02 , H04L12/861
摘要： A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

10. 发明授权

US11804270B2 Non-volatile memory device 有权
公开(公告)号：US11804270B2
公开(公告)日：2023-10-31
申请号：US17460954
申请日：2021-08-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ji-Yeon Shin , Jeong-Don Ihm , Byung-Hoon Jeong , Jung-June Park
IPC分类号： G11C16/30 , G11C7/10 , G11C16/26 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： G11C16/30 , G11C7/1051 , G11C16/26 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
摘要： A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

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