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1. 发明授权

US07564716B2 Memory device with retained indicator of read reference level 有权
标题翻译：具有读参考电平保持指示的存储器
公开(公告)号：US07564716B2
公开(公告)日：2009-07-21
申请号：US11560554
申请日：2006-11-16
申请人： Ronald J. Syzdek , David W. Chrudimsky , Xiaojie He
发明人： Ronald J. Syzdek , David W. Chrudimsky , Xiaojie He
IPC分类号： G11C11/34
CPC分类号： G11C16/28
摘要： A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.
摘要翻译：为非易失性存储器阵列的一组位单元确定多个读取参考的读取参考电平。读取参考电平的指示符存储在与该位单元组相关联的非易失性存储单元中。读取参考电平的指示符是响应于对该组单元的读取访问操作而被访问的，并且基于所读取的参考电平的指示符来感测存储在该位组单元的存储单元处的值，该位单元组的存储器位置与读访问操作相关联。

2. 发明申请

US20080117685A1 MEMORY DEVICE WITH RETAINED INDICATOR OF READ REFERENCE LEVEL 有权
标题翻译：具有读取参考电平的保持指示的存储器件
公开(公告)号：US20080117685A1
公开(公告)日：2008-05-22
申请号：US11560554
申请日：2006-11-16
申请人： Ronald J. Syzdek , David W. Chrudimsky , Xiaojie He
发明人： Ronald J. Syzdek , David W. Chrudimsky , Xiaojie He
IPC分类号： G11C16/28
CPC分类号： G11C16/28
摘要： A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.
摘要翻译：为非易失性存储器阵列的一组位单元确定多个读取参考的读取参考电平。读取参考电平的指示符存储在与该位单元组相关联的非易失性存储单元中。读取参考电平的指示符是响应于对该组单元的读取访问操作而被访问的，并且基于所读取的参考电平的指示符来感测存储在该位组单元的存储单元处的值，该位单元组的存储器位置与读访问操作相关联。

3. 发明授权

US07378872B1 Programmable logic device architecture with multiple slice types 有权
标题翻译：具有多种切片类型的可编程逻辑器件架构
公开(公告)号：US07378872B1
公开(公告)日：2008-05-27
申请号：US11445620
申请日：2006-06-02
申请人： Om P. Agrawal , Barry Britton , Xiaojie He , Sajitha Wijesuriya , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Barry Britton , Xiaojie He , Sajitha Wijesuriya , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.
摘要翻译：本文公开了系统和方法，以根据本发明的实施例提供逻辑块片段架构和可编程逻辑块架构以及控制逻辑架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块，其中至少一个可编程逻辑块具有至少第一，第二和第三逻辑块片不同的逻辑块片类型。

4. 发明授权

US07183798B1 Synchronous memory 有权
标题翻译：同步存储器
公开(公告)号：US07183798B1
公开(公告)日：2007-02-27
申请号：US11041319
申请日：2005-01-24
申请人： Xiaojie He , Sajitha Wijesuriya , Claudia Stanley , John Schadt
发明人： Xiaojie He , Sajitha Wijesuriya , Claudia Stanley , John Schadt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/1774
摘要： Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.
摘要翻译：本文公开了系统和方法，以为可编程逻辑器件内的逻辑块提供改进的存储器技术。例如，根据本发明的实施例，可编程逻辑器件包括适于接收第一和第二时钟信号的第一和第二逻辑片。可以组合第一和第二逻辑片以形成更宽更深的存储器和单端口或同步双端口存储器。

5. 发明授权

US07675321B1 Dual-slice architectures for programmable logic devices 有权
标题翻译：可编程逻辑器件的双切片架构
公开(公告)号：US07675321B1
公开(公告)日：2010-03-09
申请号：US12409757
申请日：2009-03-24
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H01L25/00 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/17728
摘要： In one embodiment of the invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within a programmable logic block. A dual-slice logic block includes a first slice including at least two lookup tables (LUTs); a second slice including at least two LUTs; and a routing circuit coupled to each of the LUTs within the first and second slices. The routing circuit is adapted to share outputs of the dual-slice logic block among the LUTs. In another embodiment of the invention, the dual-slice logic block includes a second routing circuit coupled to each of the LUTs within the first and second slices. The second routing circuit is adapted to share inputs of the dual-slice logic block among the LUTs.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件包括可编程逻辑块内的多个可编程逻辑块和多个双片逻辑块。双切片逻辑块包括包括至少两个查找表（LUT）的第一切片; 包括至少两个LUT的第二片; 以及耦合到第一和第二切片内的每个LUT的路由电路。路由电路适于在LUT之间共享双层逻辑块的输出。在本发明的另一个实施例中，双切片逻辑块包括耦合到第一和第二切片内的每个LUT的第二路由电路。第二路由电路适于在LUT之间共享双层逻辑块的输入。

6. 发明授权

US07397276B1 Logic block control architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的逻辑块控制架构
公开(公告)号：US07397276B1
公开(公告)日：2008-07-08
申请号：US11446351
申请日：2006-06-02
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.
摘要翻译：本文公开了系统和方法，以根据本发明的实施例提供逻辑块片段架构和可编程逻辑块架构以及控制逻辑架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个逻辑块片，每个逻辑块片段具有至少一个第一片和第二片，每片具有至少第一查找表。至少一个可编程逻辑块至少包括第一逻辑块片段，第二逻辑块片段和第三逻辑块片段，其中第一逻辑块片段是不同于第二逻辑块片段的逻辑块片段类型，并且第三逻辑块片是不同于第一和第二逻辑块片段的逻辑块片段类型。逻辑块片段中的至少两个逻辑块片级的控制逻辑在逻辑块片级提供捆绑和/或非捆绑控制信号的可编程逻辑块级。

7. 发明授权

US07385417B1 Dual slice architectures for programmable logic devices 有权
标题翻译：可编程逻辑器件的双切片架构
公开(公告)号：US07385417B1
公开(公告)日：2008-06-10
申请号：US11446542
申请日：2006-06-02
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.
摘要翻译：本文公开了系统和方法，以根据本发明的实施例提供双切片架构和可编程逻辑块结构以及控制逻辑架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个双层逻辑块，其中每个双层逻辑块包括第一和第二切片，其每个具有至少第一查找表，其中第一个双逻辑块逻辑块的逻辑块片类型与第二个双片逻辑块不同，与第一和第二双层逻辑块不同的逻辑块片类型的双片逻辑块。

8. 发明授权

US08175528B2 Wireless mass storage flash memory 有权
标题翻译：无线大容量存储闪存
公开(公告)号：US08175528B2
公开(公告)日：2012-05-08
申请号：US12050544
申请日：2008-03-18
申请人： Xiaojie He , Gregory Racino
发明人： Xiaojie He , Gregory Racino
IPC分类号： H04B7/00
CPC分类号： H04L63/0853 , G06F12/1458 , H04L63/0428 , H04W12/06
摘要： Systems and/or methods are presented that can facilitate access of a memory device by the use of wireless communication technologies. A memory module is presented which combines memory with a wireless adapter component and a memory controller component to facilitate the wireless transmission and reception of data and/or commands from and to host component that requests access to the memory and the data stored therein. The memory module can dynamically switch between one wireless communication technology to another based on signal strength, signal quality, the distance between the memory module and a host component, power usage, as well as other criteria to facilitate an optimal data transmission or throughput rate.
摘要翻译：呈现了可以通过使用无线通信技术来促进对存储器件的访问的系统和/或方法。提出了一种存储器模块，其将存储器与无线适配器组件和存储器控制器组件相结合，以便于无线传输和接收来自主机组件的数据和/或命令，该组件请求对存储器和存储在其中的数据的访问。存储器模块可以基于信号强度，信号质量，存储器模块与主机组件之间的距离，功率使用以及促进最佳数据传输或吞吐速率的其它标准来动态地在一个无线通信技术之间切换到另一个。

9. 发明授权

US07696784B1 Programmable logic device with multiple slice types 有权
标题翻译：具有多种切片类型的可编程逻辑器件
公开(公告)号：US07696784B1
公开(公告)日：2010-04-13
申请号：US12105959
申请日：2008-04-18
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： In one embodiment, a programmable logic device includes a plurality of programmable logic blocks and a plurality of slices within each of the programmable logic blocks. At least one programmable logic blocks includes a first slice not adapted to provide register functionality or RAM functionality, a second slice adapted to provide register functionality but not RAM functionality, and a third slice adapted to provide register functionality and RAM functionality. Control logic within the programmable logic block is adapted to provide control signals at the programmable block level and at the slice level.
摘要翻译：在一个实施例中，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个片。至少一个可编程逻辑块包括不适于提供寄存器功能或RAM功能的第一片，适于提供寄存器功能而不是RAM功能的第二片，以及适于提供寄存器功能和RAM功能的第三片。可编程逻辑块内的控制逻辑适于在可编程块级和限幅级提供控制信号。

10. 发明授权

US07592834B1 Logic block control architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的逻辑块控制架构
公开(公告)号：US07592834B1
公开(公告)日：2009-09-22
申请号：US12164265
申请日：2008-06-30
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17728
摘要： In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件包括适于存储配置数据和多个可编程逻辑块的配置存储器。至少一个可编程逻辑块包括多个双切片逻辑块，每个双切片逻辑块包括第一和第二切片，每个切片包括至少两个查找表（LUT）和寄存器。可编程逻辑块还包括适于在可编程块级别，双切片块级别和寄存器级别分别选择控制信号的控制逻辑，该控制逻辑响应于存储在配置存储器内的配置数据。

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