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1. 发明申请

US20050273744A1 IC TILING PATTERN METHOD, IC SO FORMED AND ANALYSIS METHOD 有权
标题翻译： IC TILING PATTERN方法，IC形成和分析方法
公开(公告)号：US20050273744A1
公开(公告)日：2005-12-08
申请号：US11160339
申请日：2005-06-20
申请人： Robert Allen , John Cohn , Peter Habitz , William Leipold , Ivan Wemple , Paul Zuchowski
发明人： Robert Allen , John Cohn , Peter Habitz , William Leipold , Ivan Wemple , Paul Zuchowski
IPC分类号： G06F9/45 , G06F13/00 , G06F17/50 , H01L21/321 , H01L23/48 , H01L23/52 , H01L23/528 , H01L23/535 , H01L27/02
CPC分类号： G06F17/5068 , H01L21/3212 , H01L27/0207
摘要： The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.
摘要翻译：本发明提供一种用于提供集成电路（6）的方法，所述集成电路（6）在IC的非正交角的部分（10,12,14和16）之间具有基本均匀的密度。特别地，本发明提供了基本上平行于电气结构定向的填充平铺图案（32,34），而不管其角度如何。还提供了基于该规定的电分析方法，相关程序产品也是如此。

2. 发明申请

US20080018872A1 METHOD AND APPARATUS FOR MANUFACTURING DIAMOND SHAPED CHIPS 有权
标题翻译：用于制造金刚石型材的方法和装置
公开(公告)号：US20080018872A1
公开(公告)日：2008-01-24
申请号：US11865728
申请日：2007-10-01
申请人： Robert Allen , John Cohn , Scott Gould , Peter Habitz , Juergen Koehl , Gustavo Tellez , Ivan Wemple , Paul Zuchowski
发明人： Robert Allen , John Cohn , Scott Gould , Peter Habitz , Juergen Koehl , Gustavo Tellez , Ivan Wemple , Paul Zuchowski
IPC分类号： G03B27/42
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

3. 发明申请

US20050102117A1 ELECTROMIGRATION CHECK OF SIGNAL NETS USING NET CAPACITANCE TO EVALUATE THERMAL CHARACTERISTICS 失效
标题翻译：使用网络电容对信号网进行电气检查来评估热特性
公开(公告)号：US20050102117A1
公开(公告)日：2005-05-12
申请号：US10605990
申请日：2003-11-12
申请人： Peter Habitz
发明人： Peter Habitz
IPC分类号： G06F15/00 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method for performing an electromigration check and detecting EM problems in a device or circuit. The method uses the capacitance and resistance of the conductors of the device or circuit as parameters in determining a power limit that maintains a required temperature environment that ensures the reliability of the device or circuit. The parameters of resistance and capacitance can be determined for the device or circuit through the use of commercially available device data or simulation and analysis tools. The power limit is then used to check each device interconnect to identify the location of potential EM problems. Corrective action is taken to avoid EM problems as they are detected in the device or circuit.
摘要翻译：一种用于执行电迁移检查和检测装置或电路中的EM问题的方法。该方法使用器件或电路的导体的电容和电阻作为确定功率限制的参数，维持所需的温度环境，以确保器件或电路的可靠性。可以通过使用市售设备数据或仿真和分析工具来确定器件或电路的电阻和电容参数。然后使用功率限制来检查每个设备互连以识别潜在EM问题的位置。采取纠正措施以避免在设备或电路中检测到EM问题。

4. 发明申请

US20070050164A1 RING OSCILLATOR STRUCTURE AND METHOD OF SEPARATING RANDOM AND SYSTEMATIC TOLERANCE VALUES 失效
标题翻译：环振荡器结构和分离随机和系统公差值的方法
公开(公告)号：US20070050164A1
公开(公告)日：2007-03-01
申请号：US11162197
申请日：2005-08-31
申请人： Peter Habitz , Jerry Hayes
发明人： Peter Habitz , Jerry Hayes
IPC分类号： G06F19/00
CPC分类号： G05B23/0221 , G01R31/2648
摘要： A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
摘要翻译：环形振荡器测试结构包括可在不同数量的级之间切换的至少两个重叠环。测量在不同位置形成的一组振荡器中的不同数量的级的延迟分布，其受到不同的系统延迟效应的影响。分析延迟分布，分析系统和随机贡献与分布的标准偏差。

5. 发明申请

US20060248488A1 METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION 有权
标题翻译：在过程变化存在下产生匹配延迟的接线方法
公开(公告)号：US20060248488A1
公开(公告)日：2006-11-02
申请号：US10908102
申请日：2005-04-27
申请人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

6. 发明申请

US20060248485A1 PRIORTIZING OF NETS FOR COUPLED NOISE ANALYSIS 失效
标题翻译：联网噪声分析网络优化
公开(公告)号：US20060248485A1
公开(公告)日：2006-11-02
申请号：US10908101
申请日：2005-04-27
申请人： Eric Foreman , Peter Habitz , Gregory Schaeffer
发明人： Eric Foreman , Peter Habitz , Gregory Schaeffer
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.
摘要翻译：一种执行微电子芯片定时分析的系统和方法，其中所述方法包括识别芯片中的故障定时路径; 根据每个定时路径中发生的随机噪声事件的大小对芯片中的故障定时路径进行优先级排序; 归因于每个定时路径中发生的所有但最高阶随机噪声事件的松弛信用统计; 以及基于优先顺序的故障定时路径和松弛信用统计量来计算最坏情况的定时路径情景。优选地，随机噪声事件包括非时钟事件。此外，随机噪声事件可以包括属于不同规则组的受害者/侵略者网络组。优选地，由于芯片中发生的随机噪声事件，随机噪声事件的大小包括耦合的噪声增量延迟。

7. 发明申请

US20050246116A1 METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT 失效
标题翻译：用于评估集成电路中的时序的方法和系统
公开(公告)号：US20050246116A1
公开(公告)日：2005-11-03
申请号：US10709361
申请日：2004-04-29
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G01M99/00 , G01R13/00 , G01R31/30
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

8. 发明申请

US20070061771A1 METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION 失效
标题翻译：用于形式分析和校正的方法
公开(公告)号：US20070061771A1
公开(公告)日：2007-03-15
申请号：US11162586
申请日：2005-09-15
申请人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
发明人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译：一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。

9. 发明申请

US20080052656A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 失效
标题翻译：对参数变化的时序分析的灵敏度
公开(公告)号：US20080052656A1
公开(公告)日：2008-02-28
申请号：US11930924
申请日：2007-10-31
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

10. 发明申请

US20070226673A1 METHOD OF REDUCING CORRECLATED COUPLING BETWEEN NETS 失效
标题翻译：减少网络之间校正耦合的方法
公开(公告)号：US20070226673A1
公开(公告)日：2007-09-27
申请号：US11277541
申请日：2006-03-27
申请人： Peter Habitz , William Livingstone
发明人： Peter Habitz , William Livingstone
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, disclosed are embodiments of an associated method of re-routing an interconnection array that incorporates identifying a victim net and at least two aggressor nets and crossing the aggressor nets so that sections of multiple aggressor nets are positioned parallel to and adjacent to the victim net in order to minimizes the impact of coupling capacitance on the victim net with minimal changes to the wiring environment.
摘要翻译：公开了用于电路的互连阵列的实施例。互连阵列包括被平行于和相邻于多个交叉侵入网络的部分定位的受害网络，从而最小化电路由于耦合电容而导致的延迟或假开关的暴露。还公开了一种重新路由互连阵列的相关联的方法的实施例，该互连阵列包括识别受害网和至少两个攻击者网并且横穿攻击网，使得多个攻击者网的部分平行于并邻近受害网以便最小化耦合电容对受害网络的影响，同时对接线环境进行最小的改变。

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