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    • 2. 发明授权
    • Transceiver interface
    • 收发器接口
    • US5182746A
    • 1993-01-26
    • US676948
    • 1991-03-28
    • Amy O. HurlbutGlen M. RileyRod G. Sinks
    • Amy O. HurlbutGlen M. RileyRod G. Sinks
    • G06F13/42H04L12/28H04L12/40H04L12/56
    • H04L12/407H04L12/2803H04L12/282H04L12/40006H04L12/413H04L12/2838H04L2012/285
    • An interface between a network cell and an associated network communications transceiver passes both network information and command/control information between the cell and the transceiver. The interface is designed to minimize the number of control lines between the cell and the transceiver. A protocol between the two devices is established to deal with configuration and error reporting as well as the passage of network data. This protocol consists of the cell and the transceiver each exchanging 8 bits of status and 8 bits of data simultaneously and continuously at rates up to 1.25 MBPS. Only a single version of cell firmware is required since a fixed amount of configuration information is sent from the cell to the transceiver, and a fixed amount of status information is returned from the transceiver to the cell.
    • 网络小区和相关联的网络通信收发器之间的接口在小区和收发机之间传递网络信息和命令/控制信息。 该接口旨在最小化单元和收发器之间的控制线的数量。 建立两个设备之间的协议来处理配置和错误报告以及网络数据的通过。 该协议由小区和收发器组成,每个高达1.25 MBPS的速率同时连续地交换8位状态和8位数据。 由于固定数量的配置信息从单元发送到收发器,因此只需要单个版本的单元固件,并且固定数量的状态信息从收发器返回到单元。
    • 4. 发明授权
    • Apparatus and method for fast I/O data transfer in an intelligent cell
    • 用于在智能电池中快速I / O数据传输的装置和方法
    • US5206935A
    • 1993-04-27
    • US675448
    • 1991-03-26
    • Rod G. SinksRobert W. Donner
    • Rod G. SinksRobert W. Donner
    • G06F13/12G06F13/32
    • G06F13/122G06F13/32
    • A specialized apparatus and method for providing fast programmed I/O for transferring information in a multi-processor environment which includes a CPU, and a memory coupled to an I/O port across an internal data bus. Multiple bytes of data are transferred in successive processing cycles to the I/O port from the memory, or from the I/O to the memory by first determining the upper limit for the number of bytes that are going to be transferred. This number and the memory start address are then stored in CPU registers. The I/O module is then checked by the CPU to see if a data byte is available from an external device. If a data byte is available, the I/O module is instructed to place the data byte on the bus for storage within the memory at the start address. The address is then incremented and the count is decremented. The above procedure is repeated until the count drops to zero, after which time the next instruction is fetched.
    • 一种用于在包括CPU的多处理器环境中提供用于传送信息的快速编程I / O的专用设备和方法,以及通过内部数据总线耦合到I / O端口的存储器。 通过首先确定要传输的字节数的上限,将多个字节的数据在连续的处理周期中从存储器传输到I / O端口,或者从I / O传送到存储器。 然后将该号码和存储器起始地址存储在CPU寄存器中。 然后由CPU检查I / O模块,以查看外部设备是否有数据字节可用。 如果数据字节可用,则指示I / O模块将数据字节放在总线上,以便在起始地址存储在存储器中。 然后,该地址递增,计数递减。 重复上述步骤,直到计数值下降到零为止,之后取下一条指令。