专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06358855B1 Clean method for recessed conductive barriers 有权
标题翻译：凹陷导电屏障的清洁方法
公开(公告)号：US06358855B1
公开(公告)日：2002-03-19
申请号：US09595795
申请日：2000-06-16
申请人： Ravikumar Ramachandran , Nicolas Nagel , Christopher C. Parks
发明人： Ravikumar Ramachandran , Nicolas Nagel , Christopher C. Parks
IPC分类号： H01L21302
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76861 , H01L21/7687 , H01L27/10855
摘要： A method for cleaning an oxidized diffusion barrier layer, in accordance with the present invention, includes providing a conductive diffusion barrier layer employed for preventing oxygen and metal diffusion therethrough and providing a wet chemical etchant including hydrofluoric acid. The diffusion barrier layer is etched with the wet chemical etchant to remove oxides from the diffusion barrier layer such that by employing the wet chemical etchant linear electrical behavior is achieved through the diffusion barrier layer.
摘要翻译：根据本发明的用于清洁氧化扩散阻挡层的方法包括提供用于防止氧和金属扩散的导电扩散阻挡层，并提供包括氢氟酸在内的湿化学蚀刻剂。用湿化学蚀刻剂蚀刻扩散阻挡层以从扩散阻挡层去除氧化物，使得通过使用湿化学蚀刻剂，通过扩散阻挡层实现线性电性能。

2. 发明授权

US07227265B2 Electroplated copper interconnection structure, process for making and electroplating bath 有权
标题翻译：电镀铜互连结构，制作工艺和电镀浴
公开(公告)号：US07227265B2
公开(公告)日：2007-06-05
申请号：US10810719
申请日：2004-03-29
申请人： Panayotis C. Andricacos , Steven H. Boettcher , Dean S. Chung , Hariklia Deligianni , James E. Fluegel , Wilma Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Christopher C. Parks , Soon-Cheon Seo , Andrew H. Simon , Erick G. Walton
发明人： Panayotis C. Andricacos , Steven H. Boettcher , Dean S. Chung , Hariklia Deligianni , James E. Fluegel , Wilma Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Christopher C. Parks , Soon-Cheon Seo , Andrew H. Simon , Erick G. Walton
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/2885 , C25D3/38 , C25D5/024 , C25D5/18 , C25D7/123 , H01L21/76877
摘要： Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 μm and via openings filled with electroplated copper than is substantially free of internal seams or voids.
摘要翻译：使用包含溶解的铜盐的电镀铜浴获得至少基本上不含内部接缝或空隙的铜导体的互连结构，其中盐的浓度为酸的至少约0.4摩尔浓度至高达约0.5摩尔浓度。还提供了具有大于约3的宽高比和小于约0.275μm的宽度的铜镶嵌结构以及填充有电镀铜的通孔，基本上不含内部接缝或空隙。

3. 发明授权

US06399434B1 Doped structures containing diffusion barriers 失效
标题翻译：含有扩散阻挡层的掺杂结构
公开(公告)号：US06399434B1
公开(公告)日：2002-06-04
申请号：US09559880
申请日：2000-04-26
申请人： Susan E. Chaloux , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Christopher C. Parks , Paul Parries , Paul A. Ronsheim , Jean-Marc Rousseau
发明人： Susan E. Chaloux , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Christopher C. Parks , Paul Parries , Paul A. Ronsheim , Jean-Marc Rousseau
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L21/28512
摘要： Semiconductor structures having improved dopant configurations are obtained by use of barrier layers containing silicon, nitrogen, and oxygen atoms and having a thickness of about 5 to 50 Å. A doped semiconductor structure with controlled dopant configuration can be formed by: (a) providing a first semiconductor material region, (b) forming an interface layer comprising silicon, oxygen, and nitrogen on the first region, (c) forming a second semiconductor material region on the interface layer, the second semiconductor material region being on an opposite side of the interface layer from the first semiconductor material region, (d) providing a dopant in the second region, and (e) heating the first and second regions whereby at least a portion of the dopant diffuses from the second region through the interface layer to the first region.
摘要翻译：具有改进的掺杂剂构型的半导体结构通过使用包含硅，氮和氧原子并且具有约5至约50埃的厚度的阻挡层来获得。具有受控掺杂剂配置的掺杂半导体结构可以通过以下方式形成：（a）提供第一半导体材料区域，（b）在第一区域上形成包含硅，氧和氮的界面层，（c）形成第二半导体材料区域，所述第二半导体材料区域在与所述第一半导体材料区域的所述界面层的相对侧上，（d）在所述第二区域中提供掺杂剂，以及（e）加热所述第一区域和所述第二区域，掺杂剂的至少一部分从第二区域扩散通过界面层到第一区域。

4. 发明授权

US5998253A Method of forming a dopant outdiffusion control structure including selectively grown silicon nitride in a trench capacitor of a DRAM cell 失效
标题翻译：在DRAM单元的沟槽电容器中形成包括选择性地生长的氮化硅的掺杂剂扩散扩散控制结构的方法
公开(公告)号：US5998253A
公开(公告)日：1999-12-07
申请号：US993743
申请日：1997-12-19
申请人： Stephen K. Loh , Christine Dehm , Christopher C. Parks
发明人： Stephen K. Loh , Christine Dehm , Christopher C. Parks
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/49 , H01L21/70
CPC分类号： H01L21/8238 , H01L21/28061 , H01L29/4916 , H01L29/4933
摘要： A method for controlling dopant outdiffusion within an integrated circuit is disclosed. The method includes providing a substrate, forming a trench in the substrate, and forming a first doped layer in the trench. The first doped layer has a first dopant concentration. The method further includes forming a dopant diffusion control structure above the first doped layer. The dopant diffusion control structure includes silicon nitride (Si.sub.x N.sub.y) disposed in grain boundaries of the first doped layer. The method also includes forming a second layer above the dopant diffusion control structure. The second layer has a second dopant concentration lower than the first dopant concentration. Forming the dopant diffusion control structure includes, in one example, forming a first oxide layer over the first doped silicon layer, nitridizing the first oxide layer, thereby forming an oxynitride (SiO.sub.x N.sub.y) layer and causing the silicon nitride to migrate into the grain boundaries, and removing the oxynitride layer, thereby exposing the silicon nitride at the grain boundaries at an interface of the first doped layer.
摘要翻译：公开了一种用于控制集成电路内的掺杂物扩散扩散的方法。该方法包括提供衬底，在衬底中形成沟槽，以及在沟槽中形成第一掺杂层。第一掺杂层具有第一掺杂浓度。该方法还包括在第一掺杂层之上形成掺杂剂扩散控制结构。掺杂剂扩散控制结构包括设置在第一掺杂层的晶界中的氮化硅（SixNy）。该方法还包括在掺杂剂扩散控制结构上方形成第二层。第二层具有低于第一掺杂剂浓度的第二掺杂剂浓度。在一个示例中，形成掺杂剂扩散控制结构包括在第一掺杂硅层上形成第一氧化物层，对第一氧化物层进行氮化，从而形成氧氮化物（SiO x N y）层并使氮化硅迁移到晶界，并去除氧氮化物层，从而在第一掺杂层的界面处的晶界暴露氮化硅。

5. 发明授权

US08415772B2 Method to prevent surface decomposition of III-V compound semiconductors 有权
标题翻译：防止III-V化合物半导体表面分解的方法
公开(公告)号：US08415772B2
公开(公告)日：2013-04-09
申请号：US13570989
申请日：2012-08-09
申请人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
发明人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
IPC分类号： H01L23/58
CPC分类号： H01L21/28264 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.
摘要翻译：提供了防止III-V族化合物半导体的表面分解的方法。该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

6. 发明申请

US20120309153A1 METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS 失效
公开(公告)号：US20120309153A1
公开(公告)日：2012-12-06
申请号：US13570980
申请日：2012-08-09
申请人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
发明人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
IPC分类号： H01L21/336
CPC分类号： H01L21/28264 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

7. 发明申请

US20120086103A1 TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE 有权
标题翻译：在嵌入式动态随机访问存储器件中创建一个平板的技术
公开(公告)号：US20120086103A1
公开(公告)日：2012-04-12
申请号：US12899638
申请日：2010-10-07
申请人： ASHIMA B. CHAKRAVARTI , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
发明人： ASHIMA B. CHAKRAVARTI , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/10867 , H01L29/66181 , H01L29/945 , Y10S438/957
摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
摘要翻译：为诸如DRAM器件的半导体和/或存储器件提供了用于形成沟槽结构的方法。在一个实施例中，用于形成沟槽结构的方法包括在半导体衬底中形成沟槽，并且将沟槽的侧壁暴露于含砷气体以在沟槽的侧壁上吸附含砷层。然后将材料层沉积在沟槽的侧壁上以将含砷层包封在材料层和沟槽的侧壁之间。

8. 发明授权

US07585765B2 Formation of oxidation-resistant seed layer for interconnect applications 有权
标题翻译：形成用于互连应用的抗氧化种子层
公开(公告)号：US07585765B2
公开(公告)日：2009-09-08
申请号：US11839260
申请日：2007-08-15
申请人： Chih-Chao Yang , Nancy R. Klymko , Christopher C. Parks , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Nancy R. Klymko , Christopher C. Parks , Keith Kwong Hon Wong
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76844 , H01L21/76862 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.
摘要翻译：提供了单镶嵌型或双镶嵌型的互连结构及其形成方法，其基本上减少了将导电材料电镀到贵金属种子层上的表面氧化问题。根据本发明，使用氢等离子体处理来处理贵金属种子层，使得处理的贵金属种子层对表面氧化具有高度抗性。本发明的抗氧化贵金属种子层具有低C含量和/或低氮含量。

9. 发明授权

US08431476B2 Method to prevent surface decomposition of III-V compound semiconductors 失效
公开(公告)号：US08431476B2
公开(公告)日：2013-04-30
申请号：US13570980
申请日：2012-08-09
申请人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
发明人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： H01L21/28264 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

10. 发明申请

US20120228736A1 TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE 有权
公开(公告)号：US20120228736A1
公开(公告)日：2012-09-13
申请号：US13474790
申请日：2012-05-18
申请人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
发明人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
IPC分类号： H01L29/02 , H01L21/02 , H01L21/22
CPC分类号： H01L27/10867 , H01L29/66181 , H01L29/945 , Y10S438/957
摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式