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1. 发明授权

US06519649B1 Multi-node data processing system and communication protocol having a partial combined response 失效
标题翻译：多节点数据处理系统和具有部分组合响应的通信协议
公开(公告)号：US06519649B1
公开(公告)日：2003-02-11
申请号：US09436899
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F12/0813
摘要： A data processing system includes an interconnect and first and second nodes, coupled to the interconnect, that each include at least one agent. Each agent within the first and second nodes outputs a snoop response in response to snooping a transaction on the interconnect. Utilizing the snoop response of each agent within the first node, first response logic within the first node produces a first cumulative combined response. This first cumulative combined response is then combined by second response logic in the second node with the snoop response of each agent in the second node to produce a second cumulative combined response. After a complete combined response is obtained in this manner, the complete combined response is distributed to all nodes so that each agent can determine its response, if any, to the transaction.
摘要翻译：数据处理系统包括互连以及耦合到互连的第一和第二节点，每个包括至少一个代理。第一和第二节点内的每个代理响应于窥探互连上的事务而输出一个窥探响应。利用第一节点内的每个代理的窥探响应，第一节点内的第一响应逻辑产生第一累积组合响应。然后，该第一累积组合响应由第二节点中的第二响应逻辑与第二节点中每个代理的窥探响应组合以产生第二累积组合响应。在以这种方式获得完整的组合响应之后，完整的组合响应被分配给所有节点，使得每个代理可以确定其对事务的响应（如果有的话）。

2. 发明授权

US06591307B1 Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response 失效
标题翻译：多节点数据处理系统和队列管理方法，其中响应于部分组合响应推测性地取消排队操作
公开(公告)号：US06591307B1
公开(公告)日：2003-07-08
申请号：US09436897
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F112
CPC分类号： G06F12/0815 , G06F12/0813 , G06F12/0831
摘要： A data processing system includes an interconnect, a plurality of nodes coupled to the interconnect that each include at least one agent, response logic within each node, and a queue. In response to snooping a transaction on the interconnect, each agent outputs a snoop response. In addition, the queue, which has an associated agent, allocates an entry to service the transaction. The response logic within each node accumulates a partial combined response of its node and any preceding node until a complete combined response for all of the plurality of nodes is obtained. However, prior to the associated agent receiving the complete combined response, the queue speculatively deallocates the entry if the partial combined response indicates that an agent other than the associated agent will service the transaction.
摘要翻译：数据处理系统包括互连，耦合到互连的多个节点，每个节点包括至少一个代理，每个节点内的响应逻辑和队列。响应在互连上窥探事务，每个代理输出一个侦听响应。此外，具有关联代理的队列分配一个条目来为事务提供服务。每个节点内的响应逻辑累积其节点和任何先前节点的部分组合响应，直到获得所有多个节点的完整组合响应。然而，在相关联的代理接收到完整的组合响应之前，如果部分组合响应指示除了相关联的代理之外的代理将服务于该事务，则队列推测性地释放该条目。

3. 发明授权

US06848003B1 Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response 失效
标题翻译：多节点数据处理系统和使用从组合响应获得的目的地ID来路由写入数据的通信协议
公开(公告)号：US06848003B1
公开(公告)日：2005-01-25
申请号：US09436901
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, where each node contains a segment of the segmented data channel and each segment is coupled to at least one other segment by destination logic. In response to snooping a write request of a master agent on the interconnect, a target agent that will service the write request places its node identifier in a snoop response. When the master agent receives the combined response, which contains the node identifier of the target agent, the master agent issues on the segmented data channel a write data transaction specifying the node identifier of the target agent as a destination identifier. In response to receipt of the write data transaction, the destination logic transmits the write data transaction to a next segment only if the destination identifier does not match a node identifier associated with a node containing a current segment.
摘要翻译：数据处理系统包括多个节点，每个节点包含至少一个代理，并且每个节点都具有相关联的节点标识符，以及分布在多个节点之间的存储器。数据处理系统还包括一个包含分段数据信道的互连，其中每个节点包含分段数据信道的一个段，并且每个段通过目的地逻辑耦合到至少一个其它段。响应于在互连上窥探主代理的写请求，将服务于写请求的目标代理将其节点标识符置于窥探响应中。当主代理接收到包含目标代理的节点标识符的组合响应时，主代理在分段数据信道上发出指定目标代理的节点标识符的写数据事务作为目的地标识符。响应于写入数据事务的接收，目的地逻辑仅在目的地标识符与与包含当前段的节点相关联的节点标识符不匹配时才将写入数据事务发送到下一个段。

4. 发明授权

US06910062B2 Method and apparatus for transmitting packets within a symmetric multiprocessor system 失效
标题翻译：用于在对称多处理器系统内传输分组的方法和装置
公开(公告)号：US06910062B2
公开(公告)日：2005-06-21
申请号：US09918812
申请日：2001-07-31
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： H04L12/42 , G06F15/17 , G06F15/16
CPC分类号： G06F15/17
摘要： The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.
摘要翻译：对称多处理器系统包括多个处理节点，每个节点具有多个代理，通过互连彼此连接。请求事务由主节点中的主代理发起到所有接收节点。生成用于与请求事务相关联的写计数器号。主代理然后等待来自接收节点的组合响应。在接收到组合响应之后，根据组合的响应，将数据分组从主代理发送到所有预期的接收节点。在发送数据分组之后，主节点中的主代理准备好发送另一请求事务以及新的写计数器号，而不需要等待来自接收节点的确认。

5. 发明授权

US06671712B1 Multi-node data processing system having a non-hierarchical interconnect architecture 有权
标题翻译：具有非分层互连架构的多节点数据处理系统
公开(公告)号：US06671712B1
公开(公告)日：2003-12-30
申请号：US09436898
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F13/4217
摘要： A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency. The non-hierarchical interconnect architecture also permits design flexibility in that the segment of the interconnect within each node can be independently implemented by a set of buses or as a switch, depending upon cost and performance considerations.
摘要翻译：数据处理系统包括多个节点，每个节点包含至少一个代理，以及节点内的代理可访问的数据存储。多个节点通过包括多个非阻塞单向地址信道和至少一个单向数据信道的非分层互连来耦合。在所有多个地址信道上分别耦合到并且窥探事务的代理只能在相关联的地址信道上发布事务。当前的非分层互连架构采用的单向信道允许高频抽运操作对于传统的双向共享系统总线是不可能的。另外，与传统分层系统相比，由于没有层间（例如，总线采集）通信延迟，与本地高速缓存未命中所产生的远程（高速缓存或主）存储器的访问延迟大大降低。非分层互连架构还允许设计灵活性，因为根据成本和性能考虑，每个节点内的互连部分可以由一组总线或开关单独地实现。

6. 发明授权

US06591321B1 Multiprocessor system bus protocol with group addresses, responses, and priorities 有权
标题翻译：具有组地址，响应和优先级的多处理器系统总线协议
公开(公告)号：US06591321B1
公开(公告)日：2003-07-08
申请号：US09437200
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of snoop responses from the bus accessible memory devices are provided. Different transfer types are provided within each of the snoop response groups. A bus master device that provides a bus master signal is designated. The bus master device receives the processor request. One of the snoop response groups and one of the transfer types are appropriately designated based on the processor request. The bus master signal is formulated from a snoop response group, a transfer type, a valid request signal, and a cache line address. The bus master signal is sent to all of the bus accessible memory devices on the cache bus line and to a combined response logic system. All of the bus accessible memory devices on the cache bus line send snoop responses in response to the bus master signal based on the designated snoop response group. The snoop responses are sent to the combined response logic system. A combined response by the combined response logic system is determined based on the appropriate combined response encoding logic determined by the designated and latched snoop response group. The combined response is sent to all of the bus accessible memory devices on the cache bus line.
摘要翻译：一种用于处理和处理处理器请求的多处理器系统总线协议系统和方法，所述多处理器系统具有被窥探的多个总线可访问存储器件。至少有一条总线。提供了来自总线可访问存储器设备的不同类型的窥探响应的侦听响应组。在每个窥探响应组中提供不同的传输类型。指定提供总线主机信号的总线主设备。总线主设备接收处理器请求。根据处理器请求适当地指定其中一个侦听响应组和传输类型之一。总线主机信号由侦听响应组，传输类型，有效请求信号和高速缓存线地址来制定。总线主机信号被发送到高速缓存总线上的所有总线可访问存储器件和组合响应逻辑系统。基于指定的窥探响应组，高速缓存总线上的所有总线可访问存储器件响应于总线主机信号发送窥探响应。侦听响应被发送到组合的响应逻辑系统。基于由指定和锁存的窥探响应组确定的适当的组合响应编码逻辑来确定组合响应逻辑系统的组合响应。组合的响应被发送到高速缓存总线上的所有总线可访问存储器件。

7. 发明授权

US06519665B1 Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request 失效
标题翻译：多节点数据处理系统和传播踩踏信号以消除先前请求的通信协议
公开(公告)号：US06519665B1
公开(公告)日：2003-02-11
申请号：US09436900
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F15/16
摘要： A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second node includes the second segment and a third agent coupled to the second segment. The first node further includes cancellation logic that, in response to the first agent issuing a request on the segmented interconnect that propagates from the first segment to the second segment and the second agent indicating ability to service the request, sends a cancellation message to the third agent instructing the third agent to ignore the request.
摘要翻译：数据处理系统至少包括第一和第二节点以及具有耦合的第一和第二段的分段互连。第一节点包括第一段和耦合到第一段的第一和第二代理，并且第二节点包括第二段和耦合到第二段的第三代理。第一节点还包括消除逻辑，响应于第一代理在从第一段传播到第二段的分段互连上发出请求，并且第二代理指示服务该请求的能力，向第三代发送取消消息代理指示第三代理人忽略该请求。

8. 发明授权

US06874063B1 System bus read data transfers with data ordering control bits 失效
公开(公告)号：US06874063B1
公开(公告)日：2005-03-29
申请号：US09436421
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Vicente Enrique Chung , Guy Lynn Guthrie , Jody Bern Joyner
发明人： Ravi Kumar Arimilli , Vicente Enrique Chung , Guy Lynn Guthrie , Jody Bern Joyner
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.

9. 发明授权

US07308536B2 System bus read data transfers with data ordering control bits 失效
标题翻译：系统总线使用数据排序控制位读取数据传输
公开(公告)号：US07308536B2
公开(公告)日：2007-12-11
申请号：US11041711
申请日：2005-01-22
申请人： Ravi Kumar Arimilli , Vicente Enrique Chung , Guy Lynn Guthrie , Jody Bern Joyner
发明人： Ravi Kumar Arimilli , Vicente Enrique Chung , Guy Lynn Guthrie , Jody Bern Joyner
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G06F12/0831
摘要： A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.
摘要翻译：一种用于向处理器通知所选择的数据传输顺序的处理器的方法。该方法包括以下步骤：将系统组件经由数据总线耦合到处理器以实现数据传输，在系统组件逻辑处确定将数据发送到处理器的顺序，以及向数据总线发出与数据，其中所选择的订单位向处理器提醒订单，并且以该顺序传送数据。在优选实施例中，系统组件是高速缓存，并且该方法可以涉及在高速缓存处接收对来自处理器的读取地址/请求的排序的偏好。高速缓存控制器或偏好顺序逻辑组件的偏好顺序逻辑通过将处理器偏好与其他偏好（包括高速缓存顺序偏好）进行比较来评估期望的顺序的偏好。选择一个偏好顺序，然后以所选顺序从高速缓存的高速缓存行检索数据。

10. 发明授权

US06535957B1 System bus read data transfers with bus utilization based data ordering 失效
标题翻译：系统总线读取数据传输与基于总线利用的数据排序
公开(公告)号：US06535957B1
公开(公告)日：2003-03-18
申请号：US09436422
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Vicente Enrique Chung , Guy Lynn Guthrie , Jody Bern Joyner
发明人： Ravi Kumar Arimilli , Vicente Enrique Chung , Guy Lynn Guthrie , Jody Bern Joyner
IPC分类号： G06F932
CPC分类号： G06F9/30043 , G06F9/30185 , G06F9/34 , G06F12/0879
摘要： A method for selecting an order of data transmittal based on system bus utilization of a data processing system. The method comprises the steps of coupling system components to a processor within the data processing system to effectuate data transfer, dynamically determining based on current system bus loading, an order in which to retrieve and transmit data from the system component to the processor, and informing the processor of the order selected by issuing to the data bus a plurality of selected order bits concurrent with the transmittal of the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is a cache and a system monitor monitors the system bus usage/loading. When a read request appears at the cache, the modified cache controller preference order logic or a preference order logic component determines the order to transmit the data wherein the order is selected to substantially optimize data bandwidth when the system bus usage is high and selected to substantially optimize data latency when system bus usage is low.
摘要翻译：一种基于数据处理系统的系统总线利用率来选择数据传输顺序的方法。该方法包括以下步骤：将系统组件耦合到数据处理系统内的处理器以实现数据传输，基于当前系统总线负载动态确定，从系统组件检索和传输数据到处理器的顺序，以及通知所述处理器通过向所述数据总线发送与所述数据的传送同时发送的多个所选顺序位而选择的所述顺序，其中所述选择的顺序位向所述处理器报告所述顺序并且所述数据以该顺序被传送。在优选实施例中，系统组件是高速缓存，系统监视器监视系统总线的使用/加载。当读取请求出现在高速缓存时，修改的高速缓存控制器偏好顺序逻辑或偏好顺序逻辑组件确定发送数据的顺序，其中当系统总线使用率高时选择该顺序以基本上优化数据带宽并且被选择为基本上当系统总线使用率低时优化数据延迟。

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