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1. 发明申请

US20030229815A1 Clock generation system 有权
标题翻译：时钟发生系统
公开(公告)号：US20030229815A1
公开(公告)日：2003-12-11
申请号：US10457149
申请日：2003-06-09
申请人： ROHM CO., LTD.
发明人： Masayu Fujiwara , Masaki Onishi
IPC分类号： G06F001/04
CPC分类号： H03L7/23 , G06F1/06 , G11B20/1403
摘要： A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the SIN ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.
摘要翻译：一种时钟发生系统，用于使用PL电路产生具有与参考时钟的参考频率具有预定比率的各个频率的第一，第二和第三参考频率时钟，使得时钟具有足够的S / 尽管SIN比值受到本底噪声的限制，第一参考频率时钟被提供给第一PLL电路以产生具有与参考时钟具有预定比率的中频的中频时钟。中频时钟被提供给第二和第三PLL电路，以分别产生具有分别具有与中频的第二和第三比率的频率的第二和第三参考频率时钟。

2. 发明申请

US20020171457A1 Method of generating a clock, a clock generation device, and electronic apparatuses having a clock generation device 失效
标题翻译：时钟生成方法，时钟生成装置以及具有时钟生成装置的电子装置
公开(公告)号：US20020171457A1
公开(公告)日：2002-11-21
申请号：US10145241
申请日：2002-05-13
申请人： ROHM CO., LTD.
发明人： Masayu Fujiwara
IPC分类号： H03B019/00
CPC分类号： H03L7/197 , H03K3/0231 , H03K4/502 , H03L7/18 , H04B15/04 , H04B2215/064 , H04B2215/067
摘要： In generating a frequency-modulated clock, a first frequency modulation (FM) signal having frequency fm1 is frequency-modulated by a second FM signal having a second frequency fm2, generating a clock modulation signal fm0. The clock generation signal fm0 is used to frequency-modulate the system clock CLK by the clock modulation signal fm0. Thus, the spectrum of the clock is doubly dispersed by the first and the second FM frequencies. As a result, peak levels at the fundamental and higher harmonic frequencies are reduced as compared with conventional clock generation device.
摘要翻译：在产生调频时钟时，具有频率fm1的第一频率调制（FM）信号由具有第二频率fm2的第二FM信号进行频率调制，产生时钟调制信号fm0。时钟产生信号fm0用于通过时钟调制信号fm0对系统时钟CLK进行频率调制。因此，时钟的频谱被第一和第二FM频率双重分散。结果，与传统的时钟发生装置相比，基波和高次谐波频率的峰值电平降低。

3. 发明申请

US20020118069A1 Reference clock generation system and device 有权
标题翻译：参考时钟生成系统和设备
公开(公告)号：US20020118069A1
公开(公告)日：2002-08-29
申请号：US10078232
申请日：2002-02-15
申请人： ROHM CO., LTD.
发明人： Masayu Fujiwara , Yasunori Kawamura
IPC分类号： H03L007/00
CPC分类号： H03L7/23 , Y10S331/02
摘要： A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock. The frequency division ratios are distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.
摘要翻译：一种时钟发生系统，具有多个PLL电路级串联连接，使得分频比分布在所述各个PLL电路级上以达到所述预定比率，第一PLL电路级接收所述第一时钟和最后一个PLL电路级输出第二时钟分频比分布成使得至少在除第一级以外的PLL电路级中，各个PLL电路级的S / N比小于与时钟生成相关联的本底噪声的S / N比系统。

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