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1. 发明申请

US20090026525A1 MEMORY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：用于制造它的记忆和方法
公开(公告)号：US20090026525A1
公开(公告)日：2009-01-29
申请号：US11872723
申请日：2007-10-16
申请人： Pin-Yao Wang , Liang-Chuan Lai , Michael Ying-li Liu
发明人： Pin-Yao Wang , Liang-Chuan Lai , Michael Ying-li Liu
IPC分类号： H01L29/788 , H01L21/44
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： A method for fabricating a memory is provided. A tunneling dielectric layer, a first conductive layer, and a mask layer are formed on a substrate. The mask layer, the first conductive layer, the tunneling dielectric layer, and the substrate are patterned to form trenches in the substrate. A passivation layer and isolation structures are formed in sequence to fill the trenches, and the etching rate of the isolation structures is greater than that of the passivation layer. After the mask layer is removed, a second conductive layer is formed on the first conductive layer. Portions of the isolation structures are removed to expose the sidewalls of the first and the second conductive layers. Further, a third conductive layer is formed on the exposed sidewalls of the first and the second conductive layers. An inter-gate dielectric layer and a control gate are formed on the substrate.
摘要翻译：提供了一种用于制造存储器的方法。在衬底上形成隧道电介质层，第一导电层和掩模层。图案化掩模层，第一导电层，隧道电介质层和衬底，以在衬底中形成沟槽。顺序地形成钝化层和隔离结构以填充沟槽，并且隔离结构的蚀刻速率大于钝化层的蚀刻速率。在去除掩模层之后，在第一导电层上形成第二导电层。去除部分隔离结构以露出第一和第二导电层的侧壁。此外，第三导电层形成在第一和第二导电层的暴露的侧壁上。栅极间介质层和控制栅极形成在衬底上。

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