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1. 发明授权

US07657726B2 Context look ahead storage structures 失效
标题翻译：前瞻性存储结构
公开(公告)号：US07657726B2
公开(公告)日：2010-02-02
申请号：US11923902
申请日：2007-10-25
申请人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G06F9/312
CPC分类号： G06F9/3806
摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.
摘要翻译：存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。第二个元结构与第一个元结构分层关联。第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。

2. 发明授权

US07337271B2 Context look ahead storage structures 失效
标题翻译：前瞻性存储结构
公开(公告)号：US07337271B2
公开(公告)日：2008-02-26
申请号：US10724815
申请日：2003-12-01
申请人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G06F9/3806
摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.
摘要翻译：存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。第二个元结构与第一个元结构分层关联。第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。

3. 发明申请

US20080215816A1 APPARATUS AND METHOD FOR FILTERING UNUSED SUB-BLOCKS IN CACHE MEMORIES 审中-公开
标题翻译：在缓存记录中过滤未使用的子块的装置和方法
公开(公告)号：US20080215816A1
公开(公告)日：2008-09-04
申请号：US12116615
申请日：2008-05-07
申请人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
发明人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0886 , G06F12/0897 , G06F12/127
摘要： A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.
摘要翻译：存储器系统和方法包括具有滤波部分和未滤波部分的高速缓存。未过滤的部分被分成块大小的分量，并且滤波的部分被划分成子块大小的分量。从未过滤部分移出的块具有缓存在过滤部分中的选定子块，用于维修请求。

4. 发明授权

US07380047B2 Apparatus and method for filtering unused sub-blocks in cache memories 有权
标题翻译：用于过滤高速缓冲存储器中未使用的子块的装置和方法
公开(公告)号：US07380047B2
公开(公告)日：2008-05-27
申请号：US10955780
申请日：2004-09-30
申请人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
发明人： Philip George Emma , Allan Mark Hartstein , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F12/0886 , G06F12/0897 , G06F12/127
摘要： A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.
摘要翻译：存储器系统和方法包括具有滤波部分和未滤波部分的高速缓存。未过滤的部分被分成块大小的分量，并且滤波的部分被划分成子块大小的分量。从未过滤部分移出的块具有缓存在过滤部分中的选定子块，用于维修请求。

5. 发明授权

US07676663B2 Method, system and program product for pipelined processor having a branch target buffer (BTB) table with a recent entry queue in parallel with the BTB table 有权
标题翻译：具有分支目标缓冲器（BTB）表的流水线处理器的方法，系统和程序产品，其中最近的入口队列与BTB表并行
公开(公告)号：US07676663B2
公开(公告)日：2010-03-09
申请号：US10796426
申请日：2004-03-09
申请人： Brian Robert Prasky , Thomas Roberts Puzak , Allan Mark Hartstein
发明人： Brian Robert Prasky , Thomas Roberts Puzak , Allan Mark Hartstein
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/325 , G06F9/381
摘要： A method and apparatus enable supplementing a Branch Target Buffer (BTB) table with a recent entry queue that prevents unnecessary removal of valuable BTB table data of multiple entries for another entry. The recent entry queue detects when the startup latency of the BTB table prevents it from asynchronously aiding the microprocessor pipeline as designed for and thereby can delay the pipeline in the required situations such that the BTB table latency on startup can be overcome. The recent entry queue provides a quick access to BTB table entries that are accessed in a tight loop pattern where the throughput of the standalone BTB table cannot track the throughput of the microprocessor execution pipeline. By using the recent entry queue, the modified BTB table processes information at the rate of the execution pipeline which provides acceleration thereof.
摘要翻译：一种方法和装置使得能够使用最近的入口队列来补充分支目标缓冲器（BTB）表，以防止不必要地去除另一条目的多个条目的有价值的BTB表数据。最近的进入队列检测BTB表的启动延迟何时阻止它异步协助微处理器管道，如此设计的，从而可以在需要的情况下延迟流水线，从而可以克服启动时的BTB表延迟。最近的入口队列可以快速访问以严格环路模式访问的BTB表条目，其中独立BTB表的吞吐量无法跟踪微处理器执行管道的吞吐量。通过使用最近的进入队列，修改后的BTB表以提供加速度的执行流水线的速率处理信息。

6. 发明授权

US6055621A Touch history table 失效
标题翻译：触摸历史记录表
公开(公告)号：US6055621A
公开(公告)日：2000-04-25
申请号：US599833
申请日：1996-02-12
申请人： Thomas Roberts Puzak
发明人： Thomas Roberts Puzak
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F9/3844
摘要： A mechanism is described that predicts the success or failure of prefetching instructions based on the previous performance of the instructions. A prefetching instruction is successful if the block of information prefetched into the cache is used by the processor before it is discarded from the cache. A prefetching instruction is unsuccessful, a failure, if the block of information prefetched into the cache is not used while in the cache. The prediction regarding the success or failure of the prefetching instruction is performed utilizing a table that records the history regarding the usefulness of each prefetch made by a prefetching instruction at a given memory location. The table is called a Touch-History-Table (THT). The THT is preferably accessed during the decode phase of each instruction using the memory location of the instruction. The table records the history of previous outcomes (success or failure) of the prefetching instruction up to the table size. If a prefetch instruction is predicted as successful then a prefetch will occur and if a prefetch instruction is predicted as unsuccessful then no prefetch will be attempted.
摘要翻译：描述了一种基于先前执行指令来预测预取指令的成功或失败的机制。如果预取到高速缓存中的信息块在从缓存中丢弃之前被处理器使用，则预取指令是成功的。如果在高速缓存中不使用预取到高速缓存中的信息块，则预取指令不成功，故障。关于预取指令的成功或失败的预测是利用记录关于由预取指令在给定存储器位置进行的每个预取的有用性的历史的表执行的。该表称为触摸历史表（THT）。优选地，在使用指令的存储器位置的每个指令的解码阶段期间访问THT。该表将预取指令的以前结果（成功或失败）的历史记录记录到表格大小。如果预取指令被预测成功，则将发生预取，并且如果预取指令被预测为不成功，则不尝试预取。

7. 发明授权

US5790823A Operand prefetch table 失效
标题翻译：操作数预取表
公开(公告)号：US5790823A
公开(公告)日：1998-08-04
申请号：US502115
申请日：1995-07-13
申请人： Thomas Roberts Puzak , Harold Stuart Stone
发明人： Thomas Roberts Puzak , Harold Stuart Stone
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30
CPC分类号： G06F9/383 , G06F12/0862 , G06F9/3455
摘要： A operand prefetching mechanism is described for a system having a cache, in addition to its normal memory. The prefetch apparatus utilizes a table that records the location of each instruction that caused an operand miss and the location of the miss. Associated with this information is the address of each instruction fetch block that contains an instruction that caused an operand miss. The table is called an Operand Prefetch Table. With each instruction block fetched from the cache a search is made of the Operand Prefetch table to determine if the instructions found in this block previously caused operand misses. If the instruction block fetched matches an entry in the Operand Prefetch Table then a prefetch for future operands can be attempted for the instructions contained within the instruction block fetch segment.
摘要翻译：对于具有高速缓存的系统，除了其正常存储器之外，还描述了操作数预取机制。预取装置利用记录导致操作数丢失的指令的位置和未命中的位置的表。与该信息相关联的是每个指令获取块的地址，该地址包含导致操作数丢失的指令。该表称为操作数预取表。对于从缓存中取出的每个指令块，搜索操作数预取表，以确定此块中发现的指令是否先前导致操作数丢失。如果读取的指令块与操作数预取表中的条目匹配，则可以针对指令块提取段中包含的指令尝试将来的操作数的预取。

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