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1. 发明申请

US20190103791A1 Motor 审中-公开
公开(公告)号：US20190103791A1
公开(公告)日：2019-04-04
申请号：US16142007
申请日：2018-09-26
申请人： Ashish Goel , Marek Jakubaszek , Petr Chmelicek
发明人： Ashish Goel , Marek Jakubaszek , Petr Chmelicek
IPC分类号： H02K15/03
摘要： Construction of a permanent magnet rotor assembly having a plurality of magnetic poles and comprising a number of magnetic pole pieces arranged in circular array. Two sets of permanent magnets—one set magnetised in circumferential direction of the rotor and the second set providing flux in axial direction of rotor, generating a magnetic flux focused through the pole piece and interacting with the magnetic flux of the stator. End-plates made of magnetic material are present such there is an axial gap between the them and the array of magnetic pole pieces. Circumferentially magnetised magnets are placed in the circumferential gaps between the pole pieces, whereas the magnets providing flux in axial direction are placed in the gaps between the array of pole pieces and end-plates.

2. 发明授权

US11005321B2 Motor 有权
公开(公告)号：US11005321B2
公开(公告)日：2021-05-11
申请号：US16174530
申请日：2018-10-30
申请人： Petr Chmelicek , Ashish Goel
发明人： Petr Chmelicek , Ashish Goel
IPC分类号： H02K21/00 , H02K1/27 , H02K19/26 , H02K19/12 , H02K1/26 , H02K16/02
摘要： The current invention relates to a magnetic pole assembly, providing flux to an air gap, comprising one or more magnetic pole pieces and one or more sources of magnetic flux. Said one or more sources of magnetic flux lie adjacent to the axial faces and circumferential faces and one of the radially inner face or radially outer face of each magnetic pole piece. Thereby to allow flux created by said one or more sources of magnetic flux to enter the one or more magnetic pole pieces in order to focus the magnetic flux of said pole piece towards and out of the radial surface not having a source of magnetic flux adjacent thereto. Such an arrangement, increases the flux density in the air gap adjacent to said radial surface not having a source of magnetic flux adjacent thereto.

3. 发明申请

US20190131838A1 Motor 审中-公开
公开(公告)号：US20190131838A1
公开(公告)日：2019-05-02
申请号：US16174574
申请日：2018-10-30
申请人： Petr Chmelicek , Ashish Goel
发明人： Petr Chmelicek , Ashish Goel
IPC分类号： H02K1/27
摘要： The current invention relates to a magnetic pole arrangement comprising a plurality of magnetic pole assembles arranged back-to-back along a longitudinally extending axis of rotation X. Each providing flux to an air gap G. Each magnetic pole assembly comprising one or more magnetic poles pieces and two components of magnetic flux. The first component of magnetic flux provided by a plurality of axially magnetised axially displaced magnets arranged in circumferentially extending arrays. The second component of magnetic flux provided by a plurality of circumferentially magnetised magnets circumferentially spaced around the axis of rotation X.

4. 发明授权

US09166595B2 Configurable flip-flop circuit 有权
标题翻译：可配置触发器电路
公开(公告)号：US09166595B2
公开(公告)日：2015-10-20
申请号：US14141469
申请日：2013-12-27
申请人： Gaurav Gupta , Shiva Belwal , Ashish Goel
发明人： Gaurav Gupta , Shiva Belwal , Ashish Goel
IPC分类号： H03K3/356 , H03K19/173 , H03K3/037
CPC分类号： H03K19/1733 , H03K3/037 , H03K3/356026 , H03K3/35606 , H03K3/356078 , H03K19/1736
摘要： A configurable flip-flop circuit has modifiable connections between its circuit elements that allow it to be modified for primary and secondary uses. For example, the flip-flop circuit can be modified to provide secondary functions of NOR and NAND gates during an implementation of an ECO. At other times, the flip-flop circuit can be used to deliver normal flip-flop functionality. A configurable latch circuit is provided that can be modified to provide an output signal or an inverted output signal. A scan circuit is provided that can provide the functionality of a multiplexer.
摘要翻译：可配置的触发器电路在其电路元件之间具有可修改的连接，允许对其进行一次和二次使用的修改。例如，触发器电路可以被修改以在ECO的实现期间提供NOR和NAND门的次要功能。在其他时间，触发器电路可用于提供正常的触发器功能。提供了可配置的锁存电路，其可以被修改以提供输出信号或反相输出信号。提供了可以提供多路复用器的功能的扫描电路。

5. 发明申请

US20060255833A1 FPGA device and method for rapid interconnect and logic testing of the same 有权
标题翻译：用于快速互连和逻辑测试的FPGA器件和方法相同
公开(公告)号：US20060255833A1
公开(公告)日：2006-11-16
申请号：US11294645
申请日：2005-12-05
申请人： Pramod Singh , Ashish Goel
发明人： Pramod Singh , Ashish Goel
IPC分类号： H03K19/177
CPC分类号： G01R31/31717 , G01R31/318519 , H03K19/1737 , H03K19/17736 , H03K19/17764
摘要： A FPGA device that includes a plurality of programmable logic blocks connected to each other through interconnect resources, one or more sets of registers connected to the interconnect resources for configuring the programmable logic blocks. Additional logic is provided with the registers for selecting an interconnect/logic block testing mode thereby enabling a rapid interconnect/logic testing.
摘要翻译：一种FPGA器件，其包括通过互连资源彼此连接的多个可编程逻辑块，连接到互连资源的一组或多组寄存器，用于配置可编程逻辑块。提供附加逻辑用于选择互连/逻辑块测试模式的寄存器，从而实现快速互连/逻辑测试。

6. 发明授权

US06661797B1 Quality of service based path selection for connection-oriented networks 有权
标题翻译：面向连接的网络的基于服务质量的路径选择
公开(公告)号：US06661797B1
公开(公告)日：2003-12-09
申请号：US09514725
申请日：2000-02-28
申请人： Ashish Goel , Deepak Kataria , Dimitris Logothetis , Kajamalai Gopalaswamy Ramakrishnan
发明人： Ashish Goel , Deepak Kataria , Dimitris Logothetis , Kajamalai Gopalaswamy Ramakrishnan
IPC分类号： H04L1228
CPC分类号： H04L45/00 , H04L45/121
摘要： Arrangements and methods for efficiently selecting an optimum connection path that meets user specified delay requirements with enhanced efficiency. In a basic aspect, a method is implemented by one of a plurality of algorithms to meet user QoS specifications. The user not only specifies a delay threshold T for the incoming request but also specifies a delay threshold tolerance &egr; for the path delay that will satisfy him. Two implementations are disclosed. The first is termed non-iterative and sets scaling factor &tgr;=min (T, (n−1)/&egr;), where n is a number of links in a shortest path, scales all the relevant delay parameters by &tgr;/T, truncates all the scaled values to integers, and uses a dynamic programming algorithm to accumulate the total of resulting link delay parameters values for each possible shortest path. The second method, termed iterative, is similar, except that it sets &tgr;
摘要翻译：有效选择满足用户指定的延迟要求并提高效率的最佳连接路径的安排和方法。在一个基本方面，一种方法由多种算法中的一种来实现，以满足用户QoS规范。用户不仅为传入请求指定了延迟阈值T，还指定了将满足他的路径延迟的延迟阈值容差ε。公开了两种实现方式。第一个称为非迭代，并设置缩放因子τt = min（T，（n-1）/ epsilon），其中n是最短路径中的链路数，将所有相关延迟参数缩放为tau / T，截断将所有缩放的值作为整数，并使用动态编程算法来累积每个可能的最短路径的结果链路延迟参数值的总和。称为迭代的第二种方法是类似的，只是它设置tau << T。然后，如果缩放，截断和累加步骤不能满足客户规格，则下一次迭代将两倍。两种方法都以计算有效的方式计算从一个源到所有目的地的路径。

7. 发明授权

US09905443B2 Reflective deposition rings and substrate processing chambers incorporating same 有权
公开(公告)号：US09905443B2
公开(公告)日：2018-02-27
申请号：US13598828
申请日：2012-08-30
申请人： Anantha K. Subramani , Joseph M. Ranish , Xiaoxiong Yuan , Ashish Goel , Joung Joo Lee
发明人： Anantha K. Subramani , Joseph M. Ranish , Xiaoxiong Yuan , Ashish Goel , Joung Joo Lee
IPC分类号： C23C14/54 , C23C16/48 , H01L21/67 , H01L21/687
CPC分类号： H01L21/67115 , C23C14/541 , C23C16/481 , H01L21/67248 , H01L21/68735 , H01L21/68742
摘要： Apparatus for improving temperature uniformity across a substrate are provided herein. In some embodiments, a deposition ring for use in a substrate processing system to process a substrate may include an annular body having a first surface, an opposing second surface, and a central opening passing through the first and second surfaces, wherein the second surface is configured to be disposed over a substrate support having a support surface to support a substrate having a given width, and wherein the opening is sized to expose a predominant portion of the support surface; and wherein the first surface includes at least one reflective portion configured to reflect heat energy toward a central axis of the annular body, wherein the at least one reflective portion has a surface area that is about 5 to about 50 percent of a total surface area of the first surface.

8. 发明授权

US09260721B2 Expression vector and methods of producing high levels of proteins 有权
标题翻译：表达载体和产生高水平蛋白质的方法
公开(公告)号：US09260721B2
公开(公告)日：2016-02-16
申请号：US13471501
申请日：2012-05-15
申请人： Arun K. Singh , Ashish Goel , Sanjeev K. Mendiratta
发明人： Arun K. Singh , Ashish Goel , Sanjeev K. Mendiratta
IPC分类号： C12N15/00 , C12N15/85 , C07K14/715
CPC分类号： C12N15/85 , C07K14/7151 , C07K2319/30 , C12N2710/10022 , C12N2710/16122 , C12N2830/42 , C12N2840/60
摘要： A process for high expression of protein of interest using an expression vector. The process comprises at least the following regulatory elements: a) a CMV promoter, or a functional variant thereof, b) an intron, c) TPL or a functional variant thereof, d) VA gene or a functional variant thereof, and e) a bovine growth hormone polyadenylation sequence or a functional variant thereof.
摘要翻译：使用表达载体高表达目标蛋白的方法。该方法至少包括以下调节元件：a）CMV启动子或其功能变体，b）内含子，c）TPL或其功能变体，d）VA基因或其功能变体，e）牛生长激素多聚腺苷酸化序列或其功能变体。

9. 发明授权

US08555226B1 Automatic verification of dependency 有权
标题翻译：自动验证依赖关系
公开(公告)号：US08555226B1
公开(公告)日：2013-10-08
申请号：US13603402
申请日：2012-09-04
申请人： Xiushan Feng , Jayanta Bhadra , Ashish Goel
发明人： Xiushan Feng , Jayanta Bhadra , Ashish Goel
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An approach is provided in which a formal verification tool sends a condition signal to a first circuit instance and to a second circuit instance, which are both instances of an electric circuit design. The formal verification tool selects a common input port and sends a first input value to the common input port of the first circuit instance and sends a second input value, which is different than the first input value, to the common input port of the second circuit instance. In turn, the first circuit instance generates a first output value and the second circuit instance generates a second instance value, which are utilized to verify dependencies between the electronic circuit's input ports and output ports.
摘要翻译：提供了一种方法，其中形式验证工具向第一电路实例和第二电路实例发送条件信号，这是电路设计的两个实例。形式验证工具选择公共输入端口并将第一输入值发送到第一电路实例的公共输入端口，并将与第一输入值不同的第二输入值发送到第二电路的公共输入端口实例。反过来，第一电路实例产生第一输出值，第二电路实例产生第二实例值，用于验证电子电路的输入端口和输出端口之间的依赖关系。

10. 发明申请

US20060022700A1 FPGA-based digital circuit for reducing readback time 有权
标题翻译：基于FPGA的数字电路，减少回读时间
公开(公告)号：US20060022700A1
公开(公告)日：2006-02-02
申请号：US11190509
申请日：2005-07-26
申请人： Ashish Goel , Davinder Aggarwal
发明人： Ashish Goel , Davinder Aggarwal
IPC分类号： H03K19/00
CPC分类号： H03K19/17764 , H03K19/17736
摘要： An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.
摘要翻译：用于减小现场可编程门阵列（FPGA）中的回读时间的改进的数字电路包括具有多个锁存器的移位寄存器和提供给锁存器的时钟和复位信号。在移位寄存器的每对锁存器之间提供互连电路，用于从期望的锁存器或锁存器提供选择性数据帧。将控制信号发生器连接到所述互连电路的控制输入端可以快速回读所选择的数据帧，从而减少调试FPGA所花费的时间。

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