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    • 7. 发明授权
    • Self-reparable semiconductor and method thereof
    • 自修复半导体及其方法
    • US07730349B2
    • 2010-06-01
    • US12074557
    • 2008-03-04
    • Sehat SutardjaPantas SutardjaWilliam Lo
    • Sehat SutardjaPantas SutardjaWilliam Lo
    • G06F11/00
    • G01R31/317G01R31/31718G01R31/3172G11C29/848H01L22/22H01L2924/0002H01L2924/00
    • A self-reparable semiconductor includes M functional units each including N sub-functional units. Each of the M functional units performs the same function. First ones of the N sub-functional units communicate with second ones of the N sub-functional units over a signal path that passes through third ones of the N sub-functional units. P spare sub-functional units are functionally interchangeable with P of the N sub-functional units. M, N and P are integers greater than one. Switching devices selectively replace at least one of the N sub-functional units of at least one of the M functional units with at least one of the P spare sub-functional units. Corresponding ones of the N sub-functional units of the M functional units perform the same function. The N sub-functional units within each of the M functional units perform different functions.
    • 自修复半导体包括各自包括N个子功能单元的M个功能单元。 每个M个功能单元执行相同的功能。 N个子功能单元中的第一个与通过N个子功能单元中的第三个的信号路径与N个子功能单元中的第二个功能单元通信。 P个备用子功能单元与N个子功能单元的P功能上可互换。 M,N和P是大于1的整数。 交换设备选择性地用至少一个P备用子功能单元替换M个功能单元中的至少一个的N个子功能单元中的至少一个。 M个功能单元的N个子功能单元中的相应的功能单元执行相同的功能。 每个M个功能单元中的N个子功能单元执行不同的功能。
    • 8. 发明授权
    • Self-reparable semiconductor and method thereof
    • 自修复半导体及其方法
    • US07313723B2
    • 2007-12-25
    • US11594312
    • 2006-11-08
    • Sehat SutardjaPantas Sutardja
    • Sehat SutardjaPantas Sutardja
    • G06F11/00
    • H01L22/22G06F11/2028G06F11/2038G06F11/2051G11C29/848H01L2924/0002H01L2924/00
    • A self-reparable semiconductor comprises first and second physical layer devices each including first and second subfunctional units that cooperate to provide first and second ports associated with a multi-bit Gigabit physical layer device. A first spare physical layer device includes first and second subfunctional units. The first sub-functional units are functionally interchangeable. The second sub-functional units are functionally interchangeable. Switching devices communicate with the first and second subfunctional units of the first, second and first spare physical layer devices and replace at least one of the first and second sub-functional units of at least one of the first and second physical layer devices with at least one of the first and second sub-functional units of the first spare physical layer device when the at least one of the first and second sub-functional units is non-operable.
    • 自修复半导体包括第一和第二物理层设备,每个物理层设备包括协作以提供与多比特千兆位物理层设备相关联的第一和第二端口的第一和第二子功能单元。 第一备用物理层设备包括第一和第二子功能单元。 第一个子功能单元在功能上是可互换的。 第二子功能单元在功能上是可互换的。 交换设备与第一,第二和第一备用物理层设备的第一和第二子功能单元通信,并且至少替换第一和第二物理层设备中的至少一个的第一和第二子功能单元中的至少一个, 当第一和第二子功能单元中的至少一个不可操作时,第一备用物理层设备的第一和第二子功能单元之一。
    • 10. 发明授权
    • Ripple carry logic ASND method
    • 纹波进位逻辑ASND方法
    • US5764718A
    • 1998-06-09
    • US847933
    • 1997-04-28
    • Sehat SutardjaPantas Sutardja
    • Sehat SutardjaPantas Sutardja
    • G11C19/00G11C21/00
    • G11C21/005G11C19/00
    • Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval, and carry output signals from preceding logic stages are supplied to carry inputs of successive logic stages without additional delays following the processing delay interval of each preceding logic stage.
    • 用于逻辑地处理表示多位数位的多位的信号的装置和方法包括:将输入寄存器之间的延迟间隔连续地延迟从相关联的输入寄存器到逻辑处理级的应用,该延迟间隔基本上等于处理延迟间隔 每个位级处理阶段。 以这种方式,在逻辑处理的多个数字中的每一个的连续更多有效位有效地可用于在基本上等于先前位级逻辑级的处理延迟间隔的延迟之后的每个位级逻辑级处理。 类似地,用于锁存每个位级逻辑级的逻辑输出的输出寄存器以基本上等于处理延迟间隔的连续延迟的时间间隔进行计时,并且提供来自先前逻辑级的进位输出信号以提供连续逻辑级的输入,而无需额外的延迟 遵循每个前一逻辑级的处理延迟间隔。