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1. 发明授权

US06646933B1 Method and apparatus to reduce the amount of redundant memory column and fuses associated with a memory device 有权
标题翻译：用于减少与存储器件相关联的冗余存储器列和熔丝的量的方法和装置
公开(公告)号：US06646933B1
公开(公告)日：2003-11-11
申请号：US10210525
申请日：2002-07-31
申请人： Alexander Shubat , Niranjan Behera , Izak Kense
发明人： Alexander Shubat , Niranjan Behera , Izak Kense
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C29/808
摘要： A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input circuit is coupled to the one or more defective memory columns.
摘要翻译：存在一种将第一组非冗余存储器列耦合到非冗余输入 - 输出电路并将第二组冗余存储器列耦合到冗余输入 - 输出电路的方法，系统和装置。在第二组冗余存储器列中存储的内存列数量少于非冗余存储器列中的第一组。第一个熔丝指示耦合到非冗余输入输出电路的一组非冗余存储器列中的一个或多个存储器列是否有缺陷。另外，第二保险丝耦合到第一电路。第一电路识别哪个子输入电路耦合到一个或多个有缺陷的存储器列。

2. 发明授权

US07904766B1 Statistical yield of a system-on-a-chip 有权
标题翻译：片上系统的统计收益率
公开(公告)号：US07904766B1
公开(公告)日：2011-03-08
申请号：US11951338
申请日：2007-12-06
申请人： Niranjan Behera , Alexander Shubat
发明人： Niranjan Behera , Alexander Shubat
IPC分类号： G11C29/00 , G01R31/30 , G06F11/00
CPC分类号： G11C29/4401 , G11C29/028 , G11C29/50 , G11C29/76 , G11C2029/0401
摘要： Improving statistical yield of a system-on-a-chip. The system-on-a-chip includes several memory systems. Each memory system includes a large number of memories. The memories are tested to identify any faulty memories. One or more margins of the faulty memories are then varied and the memories are then tested again.
摘要翻译：提高片上系统的统计收益。片上系统包括多个存储系统。每个存储器系统包括大量的存储器。测试记忆以识别任何错误的记忆。然后改变故障存储器的一个或多个边缘，然后再次测试存储器。

3. 发明授权

US06519202B1 Method and apparatus to change the amount of redundant memory column and fuses associated with a memory device 有权
标题翻译：用于改变与存储器件相关联的冗余存储器列和熔丝的量的方法和装置
公开(公告)号：US06519202B1
公开(公告)日：2003-02-11
申请号：US09895896
申请日：2001-06-29
申请人： Alexander Shubat , Niranjan Behera , Izak Kense
发明人： Alexander Shubat , Niranjan Behera , Izak Kense
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C29/808
摘要： A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first group of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input-output circuit is coupled to the one or more defective memory columns.
摘要翻译：存在一种将第一组非冗余存储器列耦合到非冗余输入 - 输出电路并将第二组冗余存储器列耦合到冗余输入 - 输出电路的方法，系统和装置。在第二组冗余内存列中存储的内存列数量少于第一组非冗余内存列。第一个熔丝指示耦合到非冗余输入输出电路的一组非冗余存储器列中的一个或多个存储器列是否有缺陷。另外，第二保险丝耦合到第一电路。第一电路识别哪个子输入 - 输出电路耦合到一个或多个有缺陷的存储器列。

4. 发明授权

US07031866B1 System and method for testing a memory 有权
公开(公告)号：US07031866B1
公开(公告)日：2006-04-18
申请号：US10701545
申请日：2003-11-05
申请人： Niranjan Behera , Bruce L. Prickett, Jr.
发明人： Niranjan Behera , Bruce L. Prickett, Jr.
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G11C29/56 , G11C29/54
摘要： A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.

5. 发明申请

US20080301507A1 System and Method for Repairing a Memory 有权
标题翻译：用于修复内存的系统和方法
公开(公告)号：US20080301507A1
公开(公告)日：2008-12-04
申请号：US12188892
申请日：2008-08-08
申请人： Niranjan Behera , Bruce L. Prickett, JR. , Yervant Zorian
发明人： Niranjan Behera , Bruce L. Prickett, JR. , Yervant Zorian
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/848
摘要： A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.
摘要翻译：一种用于修复存储器的方法和系统。测试和修复包装器可操作地与存储器实例的输入/输出（I / O）电路集成，以形成可操作以从内置自身接收测试和修复信息的包装器I / O（WIO）块测试和修复（BISTR）处理器。与WIO块相关联的逻辑电路可操作地产生由BISTR处理器本地使用的用于提供修复使能控制信号的电流误差信号，以便使用冗余存储器部分修复故障存储器部分，而不必访问后处理修复签名生成的环境。

6. 发明授权

US07940550B2 Systems and methods for reducing memory array leakage in high capacity memories by selective biasing 有权
标题翻译：通过选择性偏置来减少高容量存储器中的存储器阵列泄漏的系统和方法
公开(公告)号：US07940550B2
公开(公告)日：2011-05-10
申请号：US12558816
申请日：2009-09-14
申请人： Niranjan Behera , Deepak Sabharwal , Yong Zhang
发明人： Niranjan Behera , Deepak Sabharwal , Yong Zhang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413 , G11C2207/2227
摘要： A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.
摘要翻译：用于SRAM中的泄漏减少的源极偏置机构，其中SRAM单元被布置成多个扇区。在待机模式下，多个扇区中的扇区中的SRAM单元被取消选择，并且向多个扇区的SRAM单元提供源极偏置电位。在工作模式中，提供给多个扇区中选定扇区的SRAM单元的源极偏置电位被去激活，并且读出所选扇区内的物理行中的SRAM单元，而未被选择的扇区中剩余的SRAM单元继续是源偏颇的。提供给处于待机模式的SRAM单元的源极偏置电位可以根据控制信号的逻辑状态设置为不同的电压。

7. 发明授权

US07139204B1 Method and system for testing a dual-port memory at speed in a stressed environment 有权
标题翻译：在紧张环境下以速度测试双端口存储器的方法和系统
公开(公告)号：US07139204B1
公开(公告)日：2006-11-21
申请号：US11146829
申请日：2005-06-06
申请人： Niranjan Behera
发明人： Niranjan Behera
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C8/16 , G11C2029/3602
摘要： A method and system for testing a multi-port memory cell are described. According to one embodiment of the invention, a multi-port memory device comprises an array of multi-port memory cells. Accordingly, each multi-port memory cell is connected to one word-line and two bit-lines per read/write port. The memory device includes memory testing logic to perform a first memory access operation (e.g., read/write) at a first port of the multi-port memory cell while the memory cell is in a stressed condition. For example, the first memory access operation occurs while a second memory access operation is emulated on a second port. Moreover, the memory access operations occur at a frequency that is substantially equivalent to a maximum operating frequency of the dual-port memory device.
摘要翻译：描述了用于测试多端口存储器单元的方法和系统。根据本发明的一个实施例，多端口存储器设备包括多端口存储器单元阵列。因此，每个多端口存储单元连接到每个读/写端口的一个字线和两个位线。存储器装置包括存储器测试逻辑，以在存储器单元处于应力状态时在多端口存储器单元的第一端口处执行第一存储器存取操作（例如，读/写）。例如，当在第二端口上模拟第二存储器访问操作时，发生第一存储器存取操作。此外，存储器访问操作以基本上等于双端口存储器件的最大工作频率的频率发生。

8. 发明申请

US20060190208A1 System and method for testing a memory 有权
公开(公告)号：US20060190208A1
公开(公告)日：2006-08-24
申请号：US11403783
申请日：2006-04-13
申请人： Niranjan Behera , Bruce Prickett
发明人： Niranjan Behera , Bruce Prickett
IPC分类号： G01R27/28
CPC分类号： G11C29/56 , G11C29/54
摘要： A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.

9. 发明授权

US07539590B2 System and method for testing a memory 有权
标题翻译：用于测试内存的系统和方法
公开(公告)号：US07539590B2
公开(公告)日：2009-05-26
申请号：US11403783
申请日：2006-04-13
申请人： Niranjan Behera , Bruce L. Prickett, Jr.
发明人： Niranjan Behera , Bruce L. Prickett, Jr.
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G11C29/56 , G11C29/54
摘要： A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.
摘要翻译：一种用于以速度测试存储器的方法和装置。与内存实例集成的测试和修复包装器可操作以接收从内置自检和修复（BISTR）处理器扫描的测试信息。与测试和修复包装器相关联的逻辑电路可操作以基于扫描的测试信息产生地址，数据和命令信号，其中所述信号用于实现关于存储器实例的一个或多个测试。

10. 发明申请

US20110063893A1 SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING 有权
标题翻译：通过选择性偏移减少高容量存储器中的存储器阵列泄漏的系统和方法
公开(公告)号：US20110063893A1
公开(公告)日：2011-03-17
申请号：US12558816
申请日：2009-09-14
申请人： Niranjan Behera , Deepak Sabharwal , Yong Zhang
发明人： Niranjan Behera , Deepak Sabharwal , Yong Zhang
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C11/412 , G11C11/413 , G11C2207/2227
摘要： A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.
摘要翻译：用于SRAM中的泄漏减少的源极偏置机构，其中SRAM单元被布置成多个扇区。在待机模式下，多个扇区中的扇区中的SRAM单元被取消选择，并且向多个扇区的SRAM单元提供源极偏置电位。在工作模式中，提供给多个扇区中选定扇区的SRAM单元的源极偏置电位被去激活，并且读出所选扇区内的物理行中的SRAM单元，而未被选择的扇区中剩余的SRAM单元继续是源偏颇的。提供给处于待机模式的SRAM单元的源极偏置电位可以根据控制信号的逻辑状态设置为不同的电压。

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