专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08465909B2 Self-aligned masking for solar cell manufacture 失效
标题翻译：用于太阳能电池制造的自对准掩模
公开(公告)号：US08465909B2
公开(公告)日：2013-06-18
申请号：US12916993
申请日：2010-11-01
申请人： Nicholas P. T. Bateman , Helen L. Maynard , Benjamin B. Riordon , Christopher R. Hatem , Deepak Ramappa
发明人： Nicholas P. T. Bateman , Helen L. Maynard , Benjamin B. Riordon , Christopher R. Hatem , Deepak Ramappa
IPC分类号： G03F7/20
CPC分类号： H01L31/0682 , H01L21/266 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.
摘要翻译：使用利用非晶化和晶体硅之间的物理和化学性质差异的各种方法来产生可用于后续植入物的掩模。在一些实施方案中，使用无定形和晶体硅之间的膜生长差异来产生掩模。在其他实施例中，使用非晶硅和晶体硅之间的反射率或光吸收的差异来产生掩模。在其他实施例中，掺杂和未掺杂硅的特性的差异被用于产生掩模。

2. 发明申请

US20110104618A1 SELF-ALIGNED MASKING FOR SOLAR CELL MANUFACTURE 失效
标题翻译：用于太阳能电池制造的自对准掩模
公开(公告)号：US20110104618A1
公开(公告)日：2011-05-05
申请号：US12916993
申请日：2010-11-01
申请人： Nicholas P.T. Bateman , Helen L. Maynard , Benjamin B. Riordon , Christopher R. Hatem , Deepak Ramappa
发明人： Nicholas P.T. Bateman , Helen L. Maynard , Benjamin B. Riordon , Christopher R. Hatem , Deepak Ramappa
IPC分类号： G03F7/20 , C23C14/04
CPC分类号： H01L31/0682 , H01L21/266 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.
摘要翻译：使用利用非晶化和晶体硅之间的物理和化学性质差异的各种方法来产生可用于后续植入物的掩模。在一些实施方案中，使用无定形和晶体硅之间的膜生长差异来产生掩模。在其他实施例中，使用非晶硅和晶体硅之间的反射率或光吸收的差异来产生掩模。在其他实施例中，掺杂和未掺杂硅的特性的差异被用于产生掩模。

3. 发明申请

US20100279479A1 Formation Of Raised Source/Drain On A Strained Thin Film Implanted With Cold And/Or Molecular Carbon 审中-公开
标题翻译：在冷和/或分子碳上施加的应变薄膜上形成源/排水
公开(公告)号：US20100279479A1
公开(公告)日：2010-11-04
申请号：US12434364
申请日：2009-05-01
申请人： Christopher R. Hatem , Helen L. Maynard , Deepak A. Ramappa
发明人： Christopher R. Hatem , Helen L. Maynard , Deepak A. Ramappa
IPC分类号： H01L21/30
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26593 , H01L29/165 , H01L29/41783 , H01L29/7848
摘要： A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions.
摘要翻译：公开了一种用于增强半导体结构的沟道区域中的拉伸应力的方法。该方法包括执行一个或多个冷碳或分子碳离子注入步骤以在半导体结构内注入碳离子，以在沟道区的任一侧产生应变层。然后在应变层上方形成升高的源极/漏极区域，并且随后的离子注入步骤用于掺杂升高的源极/漏极区域。毫秒退火步骤激活应变层和升高的源极/漏极区域。应变层增强了半导体结构的沟道区域内的载流子迁移率，而凸起的源极/漏极区域最小化了由于在升高的源极/漏极区域中随后注入掺杂剂离子引起的应变层中的应变减小。

4. 发明授权

US06255221B1 Methods for running a high density plasma etcher to achieve reduced transistor device damage 有权
标题翻译：运行高密度等离子体蚀刻机以减少晶体管器件损坏的方法
公开(公告)号：US06255221B1
公开(公告)日：2001-07-03
申请号：US09215020
申请日：1998-12-17
申请人： Eric A. Hudson , Jaroslaw W. Winniczek , Joel M. Cook , Helen L. Maynard
发明人： Eric A. Hudson , Jaroslaw W. Winniczek , Joel M. Cook , Helen L. Maynard
IPC分类号： H01L2102
CPC分类号： H01L21/31116 , Y10S438/91
摘要： Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source. The pulsed application of the TCP power source is configured to etch through the dielectric layer to at least one contact via hole or open area while substantially reducing damage to the transistor gate oxides of the transistor devices.
摘要翻译：公开了用于在高密度等离子体蚀刻器中蚀刻电介质层的方法和系统。一种方法包括在电介质层上提供具有光致抗蚀剂掩模的晶片，以便限定至少一个电连接到晶片的硅衬底的接触通孔或开放区域。然后，该方法进行将晶片插入高密度等离子体蚀刻器中，并脉冲施加高密度等离子体蚀刻器的TCP电源。脉冲应用包括确定期望的蚀刻性能特性，其包括与TCP源的连续波应用相关联的光致抗蚀剂选择性和蚀刻速率。然后，选择TCP源的脉冲应用的占空比，并且缩放TCP源的脉冲应用的峰值功率，以便匹配由TCP源的连续波应用传递的周期平均功率。 TCP电源的脉冲施加被配置为通过介电层蚀刻到至少一个接触通孔或开放区域，同时基本上减少对晶体管器件的晶体管栅极氧化物的损害。

5. 发明申请

US20110086501A1 Technique for Processing a Substrate Having a Non-Planar Surface 有权
标题翻译：用于处理具有非平面表面的基板的技术
公开(公告)号：US20110086501A1
公开(公告)日：2011-04-14
申请号：US12902250
申请日：2010-10-12
申请人： George D. Papasouliotis , Vikram Singh , Heyun Yin , Helen L. Maynard , Ludovic Godet
发明人： George D. Papasouliotis , Vikram Singh , Heyun Yin , Helen L. Maynard , Ludovic Godet
IPC分类号： H01L21/30
CPC分类号： H01L21/2236 , H01J37/321 , H01J37/32706 , H01J37/32834 , H01L29/66803
摘要： A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.
摘要翻译：公开了一种处理具有水平和非水平表面的衬底的方法。使用离子注入机将基片注入颗粒。在离子注入期间，由于植入过程的性质，可以在表面上沉积膜，其中该膜的厚度在水平表面上更厚。该膜的存在可能不利地改变基材的性质。为了纠正这一点，执行第二处理步骤以去除沉积在水平表面上的膜。在一些实施例中，使用蚀刻工艺去除该膜。在一些实施方案中，材料修饰步骤用于改变包含该膜的材料的组成。该材料修饰步骤可以代替或补充蚀刻工艺。

6. 发明授权

US07279426B2 Like integrated circuit devices with different depth 有权
标题翻译：像具有不同深度的集成电路器件
公开(公告)号：US07279426B2
公开(公告)日：2007-10-09
申请号：US11162766
申请日：2005-09-22
申请人： Habib Hichri , Kimberly A. Larsen , Helen L. Maynard , Kevin S. Petrarca
发明人： Habib Hichri , Kimberly A. Larsen , Helen L. Maynard , Kevin S. Petrarca
IPC分类号： H01L21/302
CPC分类号： H01L21/02118 , H01F41/041 , H01L21/02282 , H01L21/3083 , H01L21/312 , H01L21/76816 , H01L23/522 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.
摘要翻译：本发明同时形成了类似结构和不同深度的集成电路器件，例如互连和电感器。本发明通过具有通孔和没有通孔的区域的衬底上的区域上沉积保形聚合物。同时，在具有和不具有通孔的区域中形成空腔。在具有通孔的区域中形成的空腔的深度将比在没有通孔的区域中形成的空腔更深地延伸到基底中。这是因为聚合物沿着衬底的表面不均匀地沉积，更具体地，在具有基底凹陷的区域中更薄。一旦填充有导电材料，形成在具有通孔的区域中更深地延伸到衬底中的空腔成为电感器，并且在没有通孔的区域中形成的不太深地延伸到衬底中的空穴变成互连。

7. 发明授权

US09123509B2 Techniques for plasma processing a substrate 有权
标题翻译：用于等离子体处理衬底的技术
公开(公告)号：US09123509B2
公开(公告)日：2015-09-01
申请号：US13157005
申请日：2011-06-09
申请人： George D. Papasouliotis , Kamal Hadidi , Helen L. Maynard , Ludovic Godet , Vikram Singh , Timothy J. Miller , Bernard Lindsay
发明人： George D. Papasouliotis , Kamal Hadidi , Helen L. Maynard , Ludovic Godet , Vikram Singh , Timothy J. Miller , Bernard Lindsay
IPC分类号： H01J37/32
CPC分类号： H01J37/32146 , H01J37/32412 , H01J37/3244
摘要： Techniques for plasma processing a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a method comprising introducing a feed gas proximate to a plasma source, where the feed gas may comprise a first and second species, where the first and second species have different ionization energies; providing a multi-level RF power waveform to the plasma source, where the multi-level RF power waveform has at least a first power level during a first pulse duration and a second power level during a second pulse duration, where the second power level may be different from the first power level; ionizing the first species of the feed gas during the first pulse duration; ionizing the second species during the second pulse duration; and providing a bias to the substrate during the first pulse duration.
摘要翻译：公开了用于等离子体处理衬底的技术。在一个特定的示例性实施例中，该技术可以通过包括将进料气体接近等离子体源的方法来实现，其中进料气体可以包括第一和第二物质，其中第一和第二物质具有不同的电离能; 向所述等离子体源提供多级RF功率波形，其中所述多级RF功率波形在第一脉冲持续时间期间具有至少第一功率电平，并且在第二脉冲持续时间期间具有第二功率电平，其中所述第二功率电平可以与第一功率水平不同; 在第一脉冲持续期间电离原料气体的第一种; 在第二脉冲期间电离第二物种; 以及在所述第一脉冲持续时间期间向所述衬底提供偏置。

8. 发明申请

US20120175342A1 TECHNIQUE FOR MANUFACTURING BIT PATTERNED MEDIA 有权
标题翻译：制造位图形图的技术
公开(公告)号：US20120175342A1
公开(公告)日：2012-07-12
申请号：US13342762
申请日：2012-01-03
申请人： Frank Sinclair , Julian G. Blake , Helen L. Maynard , Alexander C. Kontos
发明人： Frank Sinclair , Julian G. Blake , Helen L. Maynard , Alexander C. Kontos
IPC分类号： C23F1/00 , B05D5/12
CPC分类号： G11B5/855
摘要： A novel, technique: for manufacturing bit patterned media is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for manufacturing hit pattern media. The technique, which may be realized as a method comprising: forming a non-catalysis region on a first portion of a catalysis layer; forming a non-magnetic separator on the non-catalysis region; and forming a magnetic active region on it second portion of the catalysis layer adjacent to the first portion of the catalysis layer.
摘要翻译：公开了一种新颖的技术：用于制造位图案的介质。在一个特定的示例性实施例中，该技术可以被实现为用于制造命中图案媒体的方法。该技术可以被实现为一种方法，包括：在催化层的第一部分上形成非催化区; 在非催化区上形成非磁性分离器; 以及在催化层的与催化层的第一部分相邻的第二部分上形成磁性活性区域。

9. 发明授权

US08124487B2 Method for enhancing tensile stress and source/drain activation using Si:C 有权
标题翻译：使用Si：C增强拉应力和源/漏活化的方法
公开(公告)号：US08124487B2
公开(公告)日：2012-02-28
申请号：US12341489
申请日：2008-12-22
申请人： Helen L. Maynard , Vikram Singh , Hans-Joachim L. Gossman
发明人： Helen L. Maynard , Vikram Singh , Hans-Joachim L. Gossman
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01J37/3171 , H01J2237/24528 , H01J2237/31706 , H01L21/26513 , H01L21/26586 , H01L21/268 , H01L21/2686 , H01L29/6659 , H01L29/7848 , H01L29/7849
摘要： A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.
摘要翻译：公开了一种用于增强半导体结构的沟道区域中的拉伸应力的方法。该方法包括以预定的注入能量执行一系列离子注入步骤，以在半导体结构内部深入注入碳离子以产生应变层。使用毫秒退火工艺对应变层进行退火。随后的离子注入步骤用于用磷离子掺杂源极/漏极区域和源极/漏极延伸部分，使得掺杂区域保持在应变层上方。第二毫秒退火步骤激活源极/漏极区域和源极/漏极延伸部分。应变层增强了半导体结构的沟道区内的载流子迁移率，同时也防止了P在结构内的扩散。

10. 发明授权

US09093104B2 Technique for manufacturing bit patterned media 有权
标题翻译：技术制造位图案媒体
公开(公告)号：US09093104B2
公开(公告)日：2015-07-28
申请号：US13342762
申请日：2012-01-03
申请人： Frank Sinclair , Julian G. Blake , Helen L. Maynard , Alexander C. Kontos
发明人： Frank Sinclair , Julian G. Blake , Helen L. Maynard , Alexander C. Kontos
IPC分类号： B44C1/22 , G11B5/855
CPC分类号： G11B5/855
摘要： A novel technique for manufacturing bit patterned media is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for manufacturing bit pattern media. The technique, which may be realized as a method comprising: forming a non-catalysis region on a first portion of a catalysis layer; forming a non-magnetic separator on the non-catalysis region; and forming a magnetic active region on a second portion of the catalysis layer adjacent to the first portion of the catalysis layer.
摘要翻译：公开了一种用于制造位图案化介质的新型技术。在一个特定的示例性实施例中，该技术可以被实现为用于制造钻头图案介质的方法。该技术可以被实现为一种方法，包括：在催化层的第一部分上形成非催化区; 在非催化区上形成非磁性分离器; 以及在催化层的与催化层的第一部分相邻的第二部分上形成磁性活性区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式