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    • 6. 发明申请
    • Availability of space in a RISC microprocessor architecture
    • RISC微处理器架构中空间的可用性
    • US20070271441A1
    • 2007-11-22
    • US11881283
    • 2007-07-26
    • George ShawMartin McClurgBradley JensenRussell FishCharles Moore
    • George ShawMartin McClurgBradley JensenRussell FishCharles Moore
    • G06F15/00
    • G06F12/0875G06F9/30014G06F9/3005G06F9/30134G06F9/30145G06F9/30167G06F9/322G06F9/3824G06F9/3861G06F9/3877G06F9/3879G09G5/363G09G5/393G09G2360/121G09G2360/126
    • A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
    • 微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。 中央处理单元(CPU)指令集是硬连线的,允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动,从而提高性能。 微处理单元(MPU)包含52个通用寄存器,包括16个全局数据寄存器,一个索引寄存器,一个计数寄存器,一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。 两个堆栈都包含顶部元素中的索引寄存器,缓存在芯片上,并在需要时自动溢出并从外部存储器中重新填充。 堆栈最小化数据移动,并在过程调用,参数传递和变量赋值期间最小化存储器访问。 此外,MPU还包含一个模式/状态寄存器和41个用于I / O,控制,配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据,计数事件,测量时间和执行其他与时序相关的功能的输入输出处理器(IOP)。 零操作数堆栈架构消除了操作数位。 堆栈还可以在过程内和跨过程中最小化寄存器保存和加载,从而允许较短的指令序列和更快的运行代码。 指令简单易于解码和执行,允许MPU和IOP在单个时钟周期内发出和完成指令,每个时钟周期为100个本机MIPS峰值执行。 每次执行指令提取或预取时,CPU使用8位操作码,最多可从内存中获取四条指令。 这些指令可以重复,而不会从内存重新读取。 当直接连接到DRAM而没有高速缓存时,这将保持高性能。