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1. 发明授权

US06365512B1 Method and apparatus for a direct buried strap for same level contact interconnections for semiconductor devices 有权
标题翻译：用于半导体器件的相同电平接触互连的直接掩埋带的方法和装置
公开(公告)号：US06365512B1
公开(公告)日：2002-04-02
申请号：US09598790
申请日：2000-06-21
申请人： Michael Stetter , Frank Grellner
发明人： Michael Stetter , Frank Grellner
IPC分类号： H01L2176
CPC分类号： H01L21/76895 , H01L21/28518 , H01L27/1104
摘要： A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack on a semiconductor substrate, and forming a protective layer on sidewalls of the gate stack. The protective layer extends horizontally over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer is formed over the protective layer and in contact with a gate conductor of the gate stack and in contact with a diffusion region formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap and a silicided diffusion region in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.
摘要翻译：根据本发明的用于形成用于半导体器件的直接掩埋带的方法和装置包括在半导体衬底上形成栅极叠层，并在栅叠层的侧壁上形成保护层。保护层在半导体衬底的与栅堆叠相邻的部分上水平延伸。导电层形成在保护层上并与栅极堆叠的栅极导体接触并且与形成在与栅极导体相邻的半导体衬底中的扩散区域接触。介电层形成在导电层上，并且电介质层被图案化以暴露导电层的一部分。暴露的导电层的部分包括在栅极导体上的导电层的一部分和与栅极导体相邻的衬底的一部分。导电层的暴露区域被硅化以在衬底中形成直接掩埋带和硅化物扩散区。直接掩埋带将半导体器件的栅极导体电连接到扩散区域。

2. 发明授权

US06638851B2 Dual hardmask single damascene integration scheme in an organic low k ILD 有权
标题翻译：有机低k ILD中的双重硬掩模单镶嵌整体方案
公开(公告)号：US06638851B2
公开(公告)日：2003-10-28
申请号：US09845305
申请日：2001-05-01
申请人： Andy Cowley , Erdem Kaltalioglu , Michael Stetter
发明人： Andy Cowley , Erdem Kaltalioglu , Michael Stetter
IPC分类号： H01L214763
CPC分类号： H01L21/76802
摘要： Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD) by: providing semiconductor substrate; depositing organic low k ILD layer on substrate; forming hardmask 1 on organic low k ILD layer and forming sacrificial hardmask 2 on hardmask 1; forming a patterned photoresist layer on sacrificial hardmask 2; etching selective to sacrificial hardmask 2 and stripping photoresist; etching of hardmask 1 in which the etch is selective to the organic low k ILD layer; depositing a liner or conformal barrier layer over the substrate, organic low k ILD layer, hardmask 1 and hardmask 2; forming a plated metal layer over the liner or conformal barrier layer; and removing metal layer and removing liner with simultaneous removal of sacrificial hardmask 2 so that facets in sacrificial hardmask 2 are removed during liner/sacrificial hardmask 2 removal.
摘要翻译：在有机低k层间电介质（ILD）中的单镶嵌工艺集成方案中使用双重无机硬掩模制造半导体的工艺：提供半导体衬底;在衬底上沉积有机低k ILD层;在有机低k ILD层上形成硬掩模1; 在硬掩模1上形成牺牲硬掩模2;在牺牲硬掩模2上形成图案化的光刻胶层;对牺牲硬掩模2进行选择性蚀刻和剥离光刻胶;蚀刻硬掩模1，其中蚀刻对有机低k ILD层是选择性的;沉积衬垫或在衬底上的共形阻挡层，有机低k ILD层，硬掩模1和硬掩模2;在衬里或保形阻挡层上形成电镀金属层; 并移除金属层，同时去除牺牲性硬掩模2，从而在衬垫/牺牲硬掩模2移除期间去除牺牲硬掩模2中的刻面。

3. 发明授权

US06559042B2 Process for forming fusible links 有权
公开(公告)号：US06559042B2
公开(公告)日：2003-05-06
申请号：US09894337
申请日：2001-06-28
申请人： Hans-Joachim Barth , Lloyd G. Burrell , Gerald R. Friese , Michael Stetter
发明人： Hans-Joachim Barth , Lloyd G. Burrell , Gerald R. Friese , Michael Stetter
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

4. 发明授权

US07060619B2 Reduction of the shear stress in copper via's in organic interlayer dielectric material 有权
标题翻译：在有机层间介质材料中减少铜通道中的剪切应力
公开(公告)号：US07060619B2
公开(公告)日：2006-06-13
申请号：US10379346
申请日：2003-03-04
申请人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
发明人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.
摘要翻译：形成包含逻辑电路（微处理器，Asics或其他）或随机存取存储器单元（DRAMS）的半导体主体上的互连层以显着减少相邻导体/通孔之间的短路数量的方式形成， 0.18微米或更小。这是通过蚀刻完成的，以在化学机械抛光工艺完成后在每一层上形成凹陷的铜顶表面。在凹陷的铜表面上施加的阻挡层的厚度被控制成与周围的绝缘体表面基本上共面。较厚的阻挡层消除了对覆盖层的需要。消除覆盖层导致整体电容耦合，应力和成本的降低。

5. 发明授权

US5917193A Method and apparatus for detecting leaks in a container 失效
标题翻译：用于检测容器中的泄漏的方法和装置
公开(公告)号：US5917193A
公开(公告)日：1999-06-29
申请号：US875552
申请日：1997-07-11
申请人： Gerhart Schroff , Michael Stetter
发明人： Gerhart Schroff , Michael Stetter
IPC分类号： G01M3/24 , G01M3/38 , G01N15/06
CPC分类号： G01M3/24 , G01M3/38
摘要： The invention concerns a method and device for checking tightness of containers, housings and similar test objects (15). The test object (15) is subjected to a pressurized test gas. If a leak (28) is present, test gas escapes from the text object (15) and is exposed in a test chamber (18) to an intensity-modulated electromagnetic wave field emitted by a laser (1). The wave field contains frequency components which are absorbed by the test gas to produce a photo-acoustic signal indicative of the presence of a leak. To facilitate a quantitative tightness examination even using a longitudinal multimode laser with several laser modes which can be absorbed by the test gas, it is proposed according to the present invention that the temperature of the laser (1) should be set to a reference value and the excitation power of the laser should be kept at a constant mean level, so that the photo-acoustic signal can be measured and evaluated as a measure of the test gas concentration in the test chamber and/or of the size of the leak from the test object. To improve measuring accuracy, a reference chamber (5) with a predetermined test gas concentration is in addition exposed to the intensity-modulated wave field emitted by the laser (1); the photo-acoustic signal (6) produced in the reference chamber (5) is then used either for standardization purposes for when the test gas concentration in the test chamber (18) is determined, or for adjusting the reference temperature value (T.sub.ref) of the laser (1) to a predetermined working point.
摘要翻译： PCT No.PCT / EP96 / 00065 Sec。 371日期1997年7月11日 102（e）1997年7月11日PCT PCT 1996年1月9日PCT公布。公开号WO96 / 21850 日期1996年7月18日本发明涉及用于检查容器，外壳和类似试验物体的紧密性的方法和装置（15）。试验对象（15）经受加压试验气体。如果存在泄漏（28），则测试气体从文本物体（15）逸出，并且在测试室（18）中暴露于由激光器（1）发射的强度调制的电磁波场。波场包含由测试气体吸收的频率分量，以产生指示泄漏的存在的光声信号。为了便于即使使用可被测试气体吸收的几种激光模式的纵向多模式激光器进行定量紧密度检查，根据本发明提出，激光器（1）的温度应设定为参考值，激光的激发功率应保持在一个恒定的平均水平，以便可以测量和评估光声信号，作为测试室中测试气体浓度的测量值和/或来自测试室的泄漏尺寸测试对象。为了提高测量精度，另外暴露于由激光器（1）发射的强度调制波场的具有预定测试气体浓度的参考室（5）; 然后在参考室（5）中产生的光声信号（6）用于标准化目的，以便当确定测试室（18）中的测试气体浓度时，或者用于调整测试室（18）中的测试气体浓度，或者用于调整测试室激光器（1）到预定的工作点。

6. 发明申请

US20060073397A1 Masking arrangement and method for producing integrated circuit arrangements 审中-公开
标题翻译：用于制造集成电路布置的屏蔽布置和方法
公开(公告)号：US20060073397A1
公开(公告)日：2006-04-06
申请号：US11244857
申请日：2005-10-06
申请人： Johannes Freund , Michael Stetter
发明人： Johannes Freund , Michael Stetter
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F9/7076 , G03F1/42 , G03F1/50 , G03F9/7003 , G03F9/7046
摘要： A masking arrangement and method for producing integrated circuit. arrangements are described. The masking arrangement includes a substrate with lithographic patterns. The lithographic patterns are arranged in different partial regions for integrated circuits that have mutually different wiring of components as well as for test patterns. Auxiliary patterns are provided for alignment of multiple lithography planes during production of one of the circuit arrangements either with or without simultaneous production of another of the circuit arrangement. The auxiliary patterns are arranged close to corners of each of the partial regions and contain alignment or overlap marks. The auxiliary patterns and the test pattern for a particular partial region form a frame around the partial region. Filling patterns are present between the partial regions.
摘要翻译：一种用于制造集成电路的掩模布置和方法。描述安排。掩模布置包括具有光刻图案的基板。对于具有相互不同的部件布线以及测试图案的集成电路，光刻图案被布置在不同的部分区域中。提供辅助图案用于在生产电路装置之一期间多个光刻平面的对准，无论是否同时生产另一个电路装置。辅助图案布置在每个部分区域的角落附近并且包含对准或重叠标记。辅助图案和特定部分区域的测试图案形成围绕部分区域的框架。填充图案存在于部分区域之间。

7. 发明授权

US06806579B2 Robust via structure and method 有权
标题翻译：坚固的通过结构和方法
公开(公告)号：US06806579B2
公开(公告)日：2004-10-19
申请号：US10364190
申请日：2003-02-11
申请人： Andy Cowley , Michael Stetter , Erdem Kaltalioglu
发明人： Andy Cowley , Michael Stetter , Erdem Kaltalioglu
IPC分类号： H01L2144
CPC分类号： H01L21/76802 , H01L21/76852 , H01L21/76877 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.
摘要翻译：在第一绝缘层中形成导线。在导电线和第一绝缘层上形成第二绝缘层。通孔延伸穿过第二绝缘层以至少接触导电线的顶表面。通孔还延伸穿过第一绝缘层以接触导电线的至少一个侧壁的至少顶部。导电线侧壁可以包括向外延伸的钩区域，使得通孔的一部分设置在导线钩区域下方，在接近导线钩区域的通孔内形成锁定区域。

8. 发明授权

US06432760B1 Method and structure to reduce the damage associated with programming electrical fuses 失效
标题翻译：减少与电气保险丝编程相关的损害的方法和结构
公开(公告)号：US06432760B1
公开(公告)日：2002-08-13
申请号：US09751475
申请日：2000-12-28
申请人： Chandrasekharan Kothandaraman , Michael Stetter , Sundar K. Iyer
发明人： Chandrasekharan Kothandaraman , Michael Stetter , Sundar K. Iyer
IPC分类号： H01L218238
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.
摘要翻译：通过形成由多晶硅层和硅化物层构成的栅极堆叠来形成集成电路（IC）结构中的改进的熔丝结构。在形成硅化物层之后，在硅化物层上沉积蚀刻停止氮化硅层。图案化氮化硅层以暴露硅化物层。在钝化的硅化物层上沉积软钝化层。软钝化层具有低热导率，其将能量限制在硅化物层中，使得对熔丝编程所需的电流最小化。软钝化层的固有延展性防止周围层产生裂纹。

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