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1. 发明授权

US5097440A Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
标题翻译：包含改进的外围电路位置和互连布置的多个存储器阵列的半导体存储器件
公开(公告)号：US5097440A
公开(公告)日：1992-03-17
申请号：US437867
申请日：1989-11-17
申请人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/401 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).
摘要翻译：半导体存储器件包括布置在一列中的八个存储器阵列（b 10a，10b）。外围电路（60）布置在八个存储器阵列（10a，10b）的中心部分中，两个列解码器（51,52）被布置在外围电路（60）之间。八个存储器阵列（10a，10b）中的每一个都具有行解码器（20）。多列第一列选择线（CL1）被设置为跨越从列解码器（51）排列在外围电路（60）一侧的三个存储器阵列（10a，10b）。另外，多列第二列选择线（CL2）被设置成与从列解码器（52）配置在外围电路（60）的另一侧的三个存储器阵列（10a，10b）相交。

2. 发明授权

US5184321A Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
标题翻译：半导体存储器件包括具有改进的外围电路位置和互连布置的多个存储器阵列
公开(公告)号：US5184321A
公开(公告)日：1993-02-02
申请号：US821875
申请日：1992-01-16
申请人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/4074 , G11C11/408
CPC分类号： G11C11/4074 , G11C11/408 , Y10S257/92
摘要： A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.
摘要翻译：多个存储器阵列（10a，10b）形成在半导体芯片（CH）上。外围电路（60）布置在多个存储器阵列（10a，10b）的中心部分。在半导体芯片（CH）的两端形成有多个焊盘（PD; p1差异p18）。多个存储器阵列（10a，10b）由预定层形成（101差异109）。要连接在多个焊盘（PD; p1 DIFFERENCE p18）和外围电路（60）之间的多个互连（L）被设置成跨越多个存储器阵列。多个互连（L）由除预定的互连层之外的层（112; 113）形成。

3. 发明授权

US4961167A Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein 失效
标题翻译：具有自动/自刷新功能的动态随机存取存储器中的衬底偏置发生器及其中产生衬底偏置的方法
公开(公告)号：US4961167A
公开(公告)日：1990-10-02
申请号：US381347
申请日：1989-07-18
申请人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/4074
CPC分类号： G11C11/4074
摘要： A dynamic random access memory with self-refresh function, which includes a substrate bias generator (100) adapted to be intermittently driven to apply a bias potential to a semiconductor substrate (15). This memory device comprises a circuit (91) for generating an internal refresh instruction signal (.phi..sub.S) in response to an external refresh instruction signal, a circuit (92, 93) which, in response to the internal refresh instruction signal, generates a refresh enable signal (.phi..sub.R) intermittently at a predetermined interval, a circuit (94, 95, 96, 98) which, in response to the refresh enable signal, refreshes data in the memory cells, and a circuit (99) which, in response to the internal refresh instruction signal and refresh enable signal, activates the substrate bias generator in the same cycle as the cycle of generation of the refresh enable signal and only for a time shorter than the cycle of generation of the refresh enable signal. The above construction contributes to a reduced power consumption in the dynamic random access memory.
摘要翻译：一种具有自刷新功能的动态随机存取存储器，其包括适于被间歇地驱动以向半导体衬底（15）施加偏置电位的衬底偏置发生器（100）。该存储装置包括用于响应于外部刷新指令信号产生内部刷新指令信号（phi S）的电路（91），响应于内部刷新指令信号产生刷新的电路（92,93）使能信号（phi R）以预定的间隔间歇地连接到响应于刷新使能信号刷新存储器单元中的数据的电路（94,95,96,98）和响应于电路（99）的电路（99）对于内部刷新指令信号和刷新使能信号，在与产生刷新使能信号的周期相同的周期中，仅在比生成刷新使能信号的周期短的时间内激活衬底偏置发生器。上述结构有助于动态随机存取存储器中的功耗降低。

4. 发明授权

US5208778A Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof 失效
标题翻译：在测试模式下可操作的动态半导体存储器件及其功能的测试方法
公开(公告)号：US5208778A
公开(公告)日：1993-05-04
申请号：US739736
申请日：1991-07-30
申请人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Takahiro Komatsu , Yoshinori Inoue
发明人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C29/36
CPC分类号： G11C29/36
摘要： A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.
摘要翻译：动态型半导体存储器件具有在多个位的存储单元上同时执行功能测试的测试模式。在测试模式下的数据写入中，从写入数据反转的数据被写入到同时选择的多个存储单元中的至少1位存储单元中，与写入数据相同的数据是写在剩余的存储单元中。在测试模式下的数据读取中，将反转数据写入的同时选择的存储单元的数据进行反转和读取，而剩余存储单元的数据原样读取。对多个位的读出数据执行逻辑处理，从而根据关于读出的数据是否为0的确定结果输出表示半导体存储器件的可接受性的逻辑值相同。

5. 发明授权

US5014246A Semiconductor memory device having shared sense amplifier and operating method thereof 失效
标题翻译：具有共享读出放大器的半导体存储器件及其操作方法
公开(公告)号：US5014246A
公开(公告)日：1991-05-07
申请号：US435901
申请日：1989-11-14
申请人： Takahiro Komatsu , Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Yoshinori Inoue
发明人： Takahiro Komatsu , Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Yoshinori Inoue
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091
CPC分类号： G11C11/4091
摘要： A memory cell array (10) is divided into four blocks. Each block comprises a memory cell array block (10aand a memory cell array block (10b). A sense amplifier block (20) is disposed between the memory cell array blocks (10a) and (10b). Each sense amplifier block (20) is connected to the memory cell array blocks (10a) and (10b) via switching circuits (80a, 80b), respectively. Four decoders (51) are provided corresponding to the four blocks. The four decoders (51) are commonly provided with a driver (52) generating a high level driving signal. Each decoder (51) is responsive to an address signal for supplying a driving signal from the driver (52) to either one of the switching circuits (80a, 80b) and for applying a ground potential to the other one of the circuits. Accordingly, the sense amplifier block (20) is connected to either one of the memory cell array blocks (10a, 10b ).
摘要翻译：存储单元阵列（10）被分成四个块。每个块包括存储单元阵列块（10a和存储单元阵列块），读出放大器块（20）设置在存储单元阵列块（10a）和（10b）之间，每个读出放大器块（20）是分别经由开关电路（80a，80b）连接到存储单元阵列块（10a）和（10b），四个解码器（51）分别对应于四个块，四个解码器（51）通常配置有驱动器（52）产生高电平驱动信号，每个解码器（51）响应于地址信号，用于将来自驱动器（52）的驱动信号提供给开关电路（80a，80b）中的任一个并且用于施加地电位因此，读出放大器块（20）连接到存储单元阵列块（10a，10b）中的任意一个。

6. 发明授权

US5010259A Voltage boosting circuit and operating method thereof 失效
标题翻译：升压电路及其工作方法
公开(公告)号：US5010259A
公开(公告)日：1991-04-23
申请号：US454580
申请日：1989-12-21
申请人： Yoshinori Inoue , Masaki Kumanoya , Takahiro Komatsu , Yasuhiro Konishi , Katsumi Dosaka
发明人： Yoshinori Inoue , Masaki Kumanoya , Takahiro Komatsu , Yasuhiro Konishi , Katsumi Dosaka
IPC分类号： G11C11/407 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H02M3/07 , H03K5/02 , H03K19/017 , H03K19/094
CPC分类号： H03K19/01714
摘要： An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.
摘要翻译：输入信号由CMOS反相器反相并提供给输出信号线。 CMOS反相器设置在电源和地之间，并且其电源侧的节点一直被充电以防止其电位降低。为输出信号线提供的输出信号被延迟电路延迟以施加到升压电容器。该升压电容器进一步提升了节点的电位。因此，输出信号的电位也得到提升。当节点的电位升高到高于电源电压时，用于充电的N沟道MOSFET关闭，以防止电荷反向流动。

7. 发明授权

US5361223A Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
标题翻译：半导体存储器件包括具有改进的外围电路位置和互连布置的多个存储器阵列
公开(公告)号：US5361223A
公开(公告)日：1994-11-01
申请号：US786320
申请日：1991-10-31
申请人： Yoshinori Inoue , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Yoshinori Inoue , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/401 , G11C11/4091 , G11C11/4097 , G11C5/02 , G11C5/06 , G11C5/14
CPC分类号： G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device comprises eight memory arrays arranged in one column. A peripheral circuit is arranged in the central portion of the eight memory arrays, two column decoders being arranged with the peripheral circuit interposed therebetween. Each of the eight memory arrays is provided with a row decoder. A plurality of first column selecting lines are provided so as to cross the three memory arrays arranged on one side of the peripheral circuit from the column decoder. In addition, a plurality of second column selecting lines are provided so as to intersect with the three memory arrays arranged on the other side of the peripheral circuit from the column decoder.
摘要翻译：半导体存储器件包括一列排列的八个存储器阵列。外围电路设置在八个存储器阵列的中心部分，两个列解码器被布置成具有插入其间的外围电路。八个存储器阵列中的每一个都具有行解码器。提供多个第一列选择线，以便从列解码器跨越布置在外围电路一侧的三个存储器阵列。此外，提供多个第二列选择线，以便与列解码器相对应地设置在外围电路另一侧的三个存储器阵列。

8. 发明授权

US08241012B2 Structure for mounting a filter in a compressor 失效
标题翻译：将过滤器安装在压缩机中的结构
公开(公告)号：US08241012B2
公开(公告)日：2012-08-14
申请号：US12324039
申请日：2008-11-26
申请人： Yoshinori Inoue , Hiroyuki Nakaima , Yoichi Takashima , Kazuya Shinmyo , Atsuo Sakagami , Masaya Sakamoto , Satoshi Umemura , Naoki Koeda , Yuji Hashimoto , Hisaya Kondo
发明人： Yoshinori Inoue , Hiroyuki Nakaima , Yoichi Takashima , Kazuya Shinmyo , Atsuo Sakagami , Masaya Sakamoto , Satoshi Umemura , Naoki Koeda , Yuji Hashimoto , Hisaya Kondo
IPC分类号： F04B53/20 , B01D35/30
CPC分类号： F04B27/109 , F04B27/1081 , F04B39/16
摘要： In a structure for mounting a filter in a compressor, a mounting member is connected to the filter. A receiving hole is formed in a housing of the compressor for receiving therein the mounting member. A first fitting portion is formed on an inner circumferential surface of a holding portion of the filter. A second fitting portion is formed on an outer circumferential surface of the mounting member for having fitting relation to the first fitting portion for an overlap distance in a radial direction of the receiving hole. When the mounting member is received in the receiving hole with the fitting relation, the filter is disposed in a fluid passage of the housing. A clearance having a dimension is formed between an outer circumferential surface of the holding portion and an inner circumferential surface of the receiving hole. Minimum value of the dimension is smaller than the overlap distance.
摘要翻译：在将过滤器安装在压缩机中的结构中，安装构件与过滤器连接。在压缩机的壳体中形成有容纳孔，用于在其中容纳安装构件。第一配合部形成在过滤器的保持部的内周面上。第二装配部分形成在安装构件的外圆周表面上，用于与接收孔的径向重叠距离与第一装配部分配合。当安装构件以接合关系容纳在接收孔中时，过滤器设置在壳体的流体通道中。在保持部的外周面和容纳孔的内周面之间形成有尺寸的间隙。尺寸的最小值小于重叠距离。

9. 发明申请

US20120132852A1 METAL ADSORBENT CONTAINING CHELATING POLYMER 有权
标题翻译：含金属吸附聚合物的金属吸附剂
公开(公告)号：US20120132852A1
公开(公告)日：2012-05-31
申请号：US13265783
申请日：2010-04-16
申请人： Yoshinori Inoue , Mitsuru Saito , Hideyuki Yanai , Waka Kamichatani
发明人： Yoshinori Inoue , Mitsuru Saito , Hideyuki Yanai , Waka Kamichatani
IPC分类号： C08G73/04 , C09K3/00
CPC分类号： B01J20/265 , B01J20/261 , B01J20/262 , B01J20/28023 , B01J20/28033 , B01J20/321 , B01J20/3217 , B01J20/3272 , B01J20/328 , B01J45/00 , B01J47/12 , B01J47/127 , B01J2220/445 , C02F1/683 , C02F2101/20 , C08G73/0206 , C08L79/02 , D01F1/10 , D01F2/08 , D01F2/30 , D01F6/50 , D01F6/54 , D01F6/94
摘要： A metal adsorbent which can adsorb a wide variety of metals, can conform to various uses, and adsorbs metals in large amounts. Metal adsorbents in various forms, which have the property of highly efficiently adsorbing metals, are produced by (a) a method in which a polyamine polymer is chemically bonded and immobilized to a porous support, (b) a method in which a polyamine polymer is blended into a solution of a raw material for fibers and the mixture is formed into fibers by wet-spinning or dry spinning, and (c) a method in which a polyamine polymer is blended into a solution of a film-forming polymer and the mixture is formed into a film by a method of film formation from solution.
摘要翻译：可以吸附多种金属的金属吸附剂可以适应各种用途，大量吸附金属。具有高效吸附金属性质的各种形式的金属吸附剂是通过（a）将多胺聚合物化学键合并固定在多孔载体上的方法制备的，（b）聚胺聚合物为混合成纤维原料的溶液，并通过湿纺或干纺法将混合物形成纤维，和（c）将聚胺聚合物混合到成膜聚合物和混合物的溶液中的方法通过从溶液中形成膜的方法形成膜。

10. 发明授权

US07959778B2 Sensor control apparatus and method 有权
标题翻译：传感器控制装置及方法
公开(公告)号：US07959778B2
公开(公告)日：2011-06-14
申请号：US11518945
申请日：2006-09-12
申请人： Hiroshi Inagaki , Yoshinori Inoue
发明人： Hiroshi Inagaki , Yoshinori Inoue
IPC分类号： G01N27/406
CPC分类号： G01N27/417
摘要： A sensor control apparatus comprising an air/fuel ratio sensor having a sensor cell with a pair of electrodes, a current source capable of supplying a predetermined current between the electrodes, a current control section that turns on/off the current source, a voltage detecting section that detects voltages generated between the electrodes at respective times when the current source is turned on and off, a differential voltage detecting section that detects a differential voltage between the voltages that are generated at the respective times when the current source is turned on and off, a first voltage comparing section that compares the differential voltage with a first threshold voltage, and a half-activated state determining section that determines that the sensor cell has reached a half-activated state when the differential voltage is lower than the first threshold voltage. A sensor control method is also provided.
摘要翻译：一种传感器控制装置，包括具有传感器单元和一对电极的空气/燃料比传感器，能够在电极之间提供预定电流的电流源，导通/截止电流源的电流控制部，电压检测检测在电流源被导通和截止的各个时刻在电极之间产生的电压的差分电压检测部分，其检测在电流源被导通和关断的各个时刻产生的电压之间的差分电压; 将差分电压与第一阈值电压进行比较的第一电压比较部，以及当所述差分电压低于所述第一阈值电压时，判定所述传感器单元已经达到半激活状态的半激活状态判定部。还提供了传感器控制方法。

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