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1. 发明授权

US6037244A Method of manufacturing a semiconductor device using advanced contact formation 失效
标题翻译：使用高级接触形成制造半导体器件的方法
公开(公告)号：US6037244A
公开(公告)日：2000-03-14
申请号：US821660
申请日：1997-03-19
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
IPC分类号： H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76895 , H01L21/76807
摘要： A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.
摘要翻译：一种通过使用柱形成与器件的有源区的接触形成半导体器件的方法。通过在半导体器件的衬底上形成一个或多个有源区并在一个有源区的至少一部分上形成柱来形成半导体器件。在基板的邻近柱的部分上设置对柱子有选择性的绝缘膜。然后使用该柱与其形成的有源区形成导电接触。在一个实施例中，柱由光致抗蚀剂形成，而在其它实施例中，柱由诸如金属的导体材料形成。有源区可以形成源/漏区或栅电极。

2. 发明授权

US06309936B1 Integrated formation of LDD and non-LDD semiconductor devices 有权
标题翻译： LDD和非LDD半导体器件的集成形成
公开(公告)号：US06309936B1
公开(公告)日：2001-10-30
申请号：US09163965
申请日：1998-09-30
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L21/823418 , H01L21/823468
摘要： A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics for the first and second gate electrodes are formed using different materials and/or having different thicknesses.
摘要翻译：形成半导体器件的方法包括在衬底上形成第一栅电极，然后在第一栅电极的至少一个侧壁上形成间隔物。在形成间隔物之后，在衬底上形成第二栅电极。将第一掺杂剂注入到衬底中以形成与间隔物相邻的第一重掺杂有源区，并与第一栅极间隔开，并与第二栅电极相邻的第二重掺杂有源区。然后去除间隔物，并将第二掺杂剂注入到衬底中以形成与第一栅电极相邻的轻掺杂有源区。在一些情况下，用于第一和第二栅电极的栅极电介质是使用不同的材料和/或具有不同的厚度来形成的。

3. 发明授权

US5942787A Small gate electrode MOSFET 失效
标题翻译：小栅极电极MOSFET
公开(公告)号：US5942787A
公开(公告)日：1999-08-24
申请号：US751582
申请日：1996-11-18
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L21/033 , H01L21/28 , H01L21/8234 , H01L21/8232
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L21/823437 , Y10S438/926 , Y10S438/947
摘要： A method of lithographically fabricating small line width features in a device in accordance with a desired pattern, the small line width features being smaller than that capable of a lithographic process alone, is disclosed. A first layer of material is provided upon a substrate, the first layer including that in which the small line width features are to be made. A lithographically patterned layer is then provided upon the first layer in accordance with a second pattern defined in conjunction with the desired pattern. The patterned layer includes a second material selected to be compatible with the material of the first layer. A conformal layer is then deposited upon the patterned layer, the conformal layer including a third material selected to be compatible in conjunction with the first material and with the second material. Sidewall spacers are formed in the conformal layer proximate side edges of the patterned layer, the sidewall spacers having a desired line width dimension of the small features to be fabricated. The patterned layer is thereafter selectively removed. The first layer is then directionally etched with a selective etch, using the sidewall spacers to prevent the etching of the first layer in accordance with the desired pattern.
摘要翻译：公开了一种根据期望的图案在装置中光刻地制造小线宽特征的方法，小线宽特征小于仅能够进行光刻工艺的小线宽特征。第一层材料设置在基板上，第一层包括将要制造小线宽特征的第一层。然后根据与期望图案一起限定的第二图案在第一层上提供光刻图案层。图案化层包括选择为与第一层的材料相容的第二材料。然后将保形层沉积在图案化层上，保形层包括选择为与第一材料和第二材料相结合的第三材料。在图案化层的近侧边缘的共形层中形成侧壁间隔物，侧壁间隔物具有要制造的小特征的期望的线宽度尺寸。此后，图案化层被选择性地去除。然后用选择性蚀刻对第一层进行定向蚀刻，使用侧壁间隔物来防止根据所需图案蚀刻第一层。

4. 发明授权

US06194283B1 High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers 失效
标题翻译：由于新的间隔填充方法包括各向异性蚀刻氮化硅间隔物，高密度沟槽填充
公开(公告)号：US06194283B1
公开(公告)日：2001-02-27
申请号：US08959587
申请日：1997-10-29
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for forming an isolation trench in a semiconductor substrate that is substantially free of voids. The method includes forming a dielectric masking layer above a semiconductor substrate. An opening is preferably formed through the masking layer and partially into the semiconductor substrate forming a shallow trench within the semiconductor substrate. Optionally, thermal oxidation of the trench may be performed to form an oxide layer within the trench. A spacer layer is preferably deposited across the exposed surface of the topography. The spacer layer is preferably etched to form spacers directly adjacent to opposed sidewall surfaces of the trench. The isolation trench may then be filled with an isolation dielectric. The presence of the spacers within the isolation trench preferably causes the lower portions of the trench to fill up faster than the upper portions. In this manner the trench may be filled without the formation of voids.
摘要翻译：一种在半导体衬底中形成基本上没有空隙的隔离沟槽的方法。该方法包括在半导体衬底上形成电介质掩模层。优选地，通过掩模层形成开口，并且部分地形成在半导体衬底内形成浅沟槽的半导体衬底中。可选地，可以进行沟槽的热氧化以在沟槽内形成氧化物层。间隔层优选沉积在地形的暴露表面上。优选蚀刻间隔层以形成与沟槽的相对侧壁表面直接相邻的间隔物。然后可以用隔离电介质填充隔离沟槽。间隔物在隔离沟槽内的存在优选地使得沟槽的下部比上部更快地填充。以这种方式，可以填充沟槽而不形成空隙。

5. 发明授权

US5929496A Method and structure for channel length reduction in insulated gate field effect transistors 失效
标题翻译：绝缘栅场效应晶体管的沟道长度减小的方法和结构
公开(公告)号：US5929496A
公开(公告)日：1999-07-27
申请号：US993767
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
IPC分类号： H01L21/223 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28194 , H01L21/223 , H01L21/26513 , H01L29/42364 , H01L29/6659
摘要： A method and structure are provided for an IGFET which has a highly scalable short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Lightly doped regions provide a graded extension or buffer region to the conduction channel. Thus, the voltage drop is shared by the source/drain and channel, in contrast to an abrupt n+/p junction where the almost the entire voltage drop occurs across the lightly doped (channel) side of the junction. This method and structure preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.
摘要翻译：提供了一种IGFET的方法和结构，其具有高度可缩放的短导电沟道长度。短通道IGFET的功能比延长的导通通道器件更快。轻掺杂区域为传导通道提供渐变的延伸或缓冲区域。因此，与突然的n + / p结相比，源/漏和沟道的电压降是共同的，其中几乎整个电压降在结点的轻掺杂（沟道）侧上发生。该方法和结构通过保护栅极免受“热电子注入”的影响来保持IGFET的完整性。该方法和结构提供IGFET具有更高的性能，而不会影响IGFET的可靠性或寿命。

6. 发明授权

US5946581A Method of manufacturing a semiconductor device by doping an active region after formation of a relatively thick oxide layer 失效
标题翻译：在形成相对厚的氧化物层之后通过掺杂有源区制造半导体器件的方法
公开(公告)号：US5946581A
公开(公告)日：1999-08-31
申请号：US780644
申请日：1997-01-08
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
IPC分类号： H01L21/336 , H01L21/768
CPC分类号： H01L29/6659 , H01L21/76814
摘要： In a semiconductor device fabrication process, an active region of the semiconductor device is formed by doping an active region after formation of a relatively thick oxide layer. According to the process, a gate electrode is formed on a substrate and a relatively thick oxide layer is formed over the gate electrode. Portions of the relatively thick oxide layer are removed to expose a region of the substrate adjacent the gate electrode. The exposed region is then doped with a dopant to form an active region. The active region may form an LDD region. The relatively thick oxide layer may comprise a contact formation layer.
摘要翻译：在半导体器件制造工艺中，半导体器件的有源区通过在形成相对厚的氧化物层之后掺杂有源区而形成。根据该工序，在基板上形成栅电极，在栅电极上形成较厚的氧化层。去除相对厚的氧化物层的部分以露出与栅电极相邻的衬底的区域。然后用暴露的区域掺杂掺杂剂以形成有源区。有源区域可以形成LDD区域。相对厚的氧化物层可以包括接触形成层。

7. 发明授权

US6114219A Method of manufacturing an isolation region in a semiconductor device using a flowable oxide-generating material 失效
标题翻译：使用可流动的氧化物发生材料制造半导体器件中的隔离区域的方法
公开(公告)号：US6114219A
公开(公告)日：2000-09-05
申请号：US929865
申请日：1997-09-15
申请人： Thomas E. Spikes, Jr. , Sey-Ping Sun , Robert Dawson
发明人： Thomas E. Spikes, Jr. , Sey-Ping Sun , Robert Dawson
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.
摘要翻译：用于制造具有沟槽隔离区域的半导体器件的方法包括在衬底中形成至少一个沟槽以限定一个或多个隔离区域。沟槽的至少一部分填充有可流动的氧化物生成材料，然后将其形成为氧化物层。可以在氧化物层上沉积可选的介电层。去除氧化物层和/或可选介电层的一部分以产生基本上平的表面。

8. 发明授权

US06458678B1 Transistor formed using a dual metal process for gate and source/drain region 失效
标题翻译：晶体管使用双金属工艺形成栅极和源极/漏极区域
公开(公告)号：US06458678B1
公开(公告)日：2002-10-01
申请号：US09625130
申请日：2000-07-25
申请人： Thomas E. Spikes, Jr. , Frederick N. Hause , David D. Wu
发明人： Thomas E. Spikes, Jr. , Frederick N. Hause , David D. Wu
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L21/823814 , H01L21/823842 , H01L29/665
摘要： A method for forming a semiconductor device includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain regions are formed in the substrate proximate the gate stack, and a first metal silicide layer is formed over the source drain regions. The thickness of the gate electrode is reduced, and a second metal silicide layer is formed over the reduced thickness gate electrode.
摘要翻译：一种形成半导体器件的方法包括提供衬底并在衬底上形成栅叠层。栅极堆叠包括具有厚度的栅电极。源极/漏极区域形成在靠近栅极堆叠的衬底中，并且在源极漏极区域上形成第一金属硅化物层。栅电极的厚度减小，并且在厚度较薄的栅电极上形成第二金属硅化物层。

9. 发明授权

US06326251B1 Method of making salicidation of source and drain regions with metal gate MOSFET 有权
标题翻译：用金属栅极MOSFET对源极和漏极区域进行腐蚀的方法
公开(公告)号：US06326251B1
公开(公告)日：2001-12-04
申请号：US09290790
申请日：1999-01-12
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28079 , H01L21/28088 , H01L21/823814 , H01L21/823835 , H01L29/495 , H01L29/66545
摘要： A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.
摘要翻译：形成晶体管的方法包括在刚刚形成衬底上的隔离和有源区域之后的初始处理阶段中形成源极/漏极注入。在介电层顶部的衬底的表面上形成均匀的氮化物层。然后沉积硅化物金属并与下面的硅反应以在源区和漏区上形成自对准硅化物。然后在硅化物的顶部上形成第二电介质层，并且形成为相对于氮化物层是选择性的。此后，去除氮化物层，然后形成最终的栅极电介质。最后，在栅极电介质的顶部形成金属栅极导体。仅在执行所有退火步骤之后才形成金属栅极导体，以防止金属通过栅极电介质尖峰，从而破坏器件。

10. 发明授权

US06239476B1 Integrated circuit isolation structure employing a protective layer and method for making same 有权
标题翻译：采用保护层的集成电路隔离结构及其制造方法
公开(公告)号：US06239476B1
公开(公告)日：2001-05-29
申请号：US09176132
申请日：1998-10-21
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A trench surface boundary is defined where the trench sidewalls intersect the upper surface of the semiconductor substrate. The trench may be filled with a trench fill material. A protective layer is then formed above the trench. The protective layer covers the trench and laterally extends above the semiconductor substrate at least a first distance beyond the trench surface boundaries.
摘要翻译：提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。限定沟槽表面边界，其中沟槽侧壁与半导体衬底的上表面相交。沟槽可以填充沟槽填充材料。然后在沟槽上方形成保护层。保护层覆盖沟槽并横向延伸超过沟槽表面边界至少第一距离半导体衬底上方。

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