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1. 发明授权

US5397735A Process for hardening active electronic components against ionizing radiations, and hardened components of large dimensions 失效
标题翻译：用于固化有源电子元件抵抗电离辐射的工艺，以及大尺寸的硬化部件
公开(公告)号：US5397735A
公开(公告)日：1995-03-14
申请号：US543796
申请日：1990-07-27
申请人： Louis Mercandalli , Didier Pribat , Bernard Dessertenne , Leonidas Karapiperis , Dominique Dieumegard
发明人： Louis Mercandalli , Didier Pribat , Bernard Dessertenne , Leonidas Karapiperis , Dominique Dieumegard
IPC分类号： H01L23/552 , H01L23/556 , H01L21/20
CPC分类号： H01L23/552 , H01L23/556 , H01L2924/0002 , Y10S438/953 , Y10S438/967
摘要： The invention relates to the "hardening" (resistance to ionizing radiations) of MOS-type components. In order to avoid the effects of these radiations (creation of electron-hole pairs), there is deposited on a substrate (1) of monocrystalline Si a layer of YSZ (2), and then a thin layer of monocrystalline Si (3). The other steps of production of the components are the same as conventional.
摘要翻译： PCT No.PCT / FR89 / 00598 Sec。 371日期1990年7月27日第 102（e）日1990年7月27日PCT 1989年11月21日提交。本发明涉及MOS型部件的“硬化”（电离辐射电阻）。为了避免这些辐射（电子 - 空穴对的产生）的影响，沉积在单晶Si的一层YSZ（2）的衬底（1）上，然后沉积一层薄的单晶Si（3）。组件的其他生产步骤与常规相同。

2. 发明授权

US5090932A Method for the fabrication of field emission type sources, and application thereof to the making of arrays of emitters 失效
标题翻译：场发射型源的制造方法及其应用于制造发射极阵列
公开(公告)号：US5090932A
公开(公告)日：1992-02-25
申请号：US439372
申请日：1989-11-16
申请人： Dominique Dieumegard , Guy Garry , Leonidas Karapiperis , Didier Pribat , Christian Collet
发明人： Dominique Dieumegard , Guy Garry , Leonidas Karapiperis , Didier Pribat , Christian Collet
IPC分类号： H01J1/304 , H01J9/02
CPC分类号： H01J1/3042 , H01J9/025
摘要： Disclosed is a method for the fabrication of field emission peaks using a monocrystalline substrate with a suitable orientation coated with an insulating layer where square-shaped elementary zones with a suitable orientation with respect to the substrate have been removed. Silicon is deposited by selective epitaxy in these zones. The epitaxial growth of silicon, at high speed parallel to the substrate and at low speed along faces of the substrate at 45.degree. to the substrate, enables the making of pyramidal peaks which, afater being coated with tungsten, form emitting peaks.
摘要翻译： PCT No.PCT / FR89 / 00142 Sec。 371日期：一九八九年十一月十六日 102（e）日期1989年11月16日PCT 1989年3月24日PCT公布。第WO89 / 09479号公报日期为1989年10月5日。公开的是使用具有涂覆有绝缘层的合适取向的单晶衬底制造场致发射峰的方法，其中具有相对于衬底的合适取向的正方形基本区被去除。在这些区域中通过选择性外延沉积硅。硅衬底的高速平行于衬底并以45°的速度沿衬底的低速外延生长使得能够形成顶部被钨涂层的锥形峰形成发光峰。

3. 发明授权

US5053833A Device made of oxide superconductive material covered with ion conductive means for adjusting the doping level and T.sub.c thereof 失效
标题翻译：氧化物超导材料的装置，其具有用于调节掺杂水平的离子传导装置和TC
公开(公告)号：US5053833A
公开(公告)日：1991-10-01
申请号：US657364
申请日：1991-02-19
申请人： Didier Pribat , Dominique Dieumegard , Guy Garry , Louis Mercandalli
发明人： Didier Pribat , Dominique Dieumegard , Guy Garry , Louis Mercandalli
IPC分类号： H01L39/12 , H01L39/24
CPC分类号： H01L39/2419 , H01L39/126 , H01L39/2454 , H01L39/2464 , Y10S505/816 , Y10T29/49982
摘要： Disclosed is a device made of superconductive material wherein the superconducting layer is enclosed by at least one material which is a conductor of ions of one of the anionic constituent elements of the superconductive layer. This makes it possible to adjust the stoichiometry of the superconductive layer. The disclosure also concerns a method for adjusting the content of the constituent elements of the superconductive layer by electrolysis.
摘要翻译：公开了一种由超导材料制成的器件，其中超导层由至少一种材料包围，该材料是超导层的阴离子构成元件之一的离子的导体。这使得可以调节超导层的化学计量。本公开还涉及通过电解调节超导层的构成元素的含量的方法。

4. 发明授权

US4952526A Method for the fabrication of an alternation of layers of monocrystalline semiconducting material and layers of insulating material 失效
标题翻译：用于制造单晶半导体材料层和绝缘材料层的交替的方法
公开(公告)号：US4952526A
公开(公告)日：1990-08-28
申请号：US333083
申请日：1989-04-04
申请人： Didier Pribat , Leonidas Karapiperis , Christian Collet , Guy Garry
发明人： Didier Pribat , Leonidas Karapiperis , Christian Collet , Guy Garry
IPC分类号： H01L21/20 , H01L21/205 , H01L21/31 , H01L21/762 , H01L21/84 , H01L27/00
CPC分类号： H01L21/76248 , H01L21/02381 , H01L21/02543 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L21/02639 , Y10S148/164
摘要： A method for making a layer of monocrystalline, semiconducting material on a layer of insulating material is disclosed. For this, epitaxial growth is achieved in a cavity closed by layers of dielectric materials, using seeds of monocrystalline, semiconducting material of a substrate. This method thus enables a 3D integration of semiconductor components.
摘要翻译：公开了一种在绝缘材料层上制造单晶半导体材料层的方法。为此，利用基底的单晶，半导体材料的种子在由介电材料层封闭的空腔中实现外延生长。因此，该方法能够实现半导体部件的3D集成。

5. 发明授权

US5294564A Method for the directed modulation of the composition or doping of semiconductors, notably for the making of planar type monolithic electronic components, use of the method and corresponding products 失效
标题翻译：用于定向调制半导体的组成或掺杂的方法，特别是用于制造平面型单片电子元件的方法及其相应产品的使用
公开(公告)号：US5294564A
公开(公告)日：1994-03-15
申请号：US28607
申请日：1993-03-08
申请人： Leonidas Karapiperis , Didier Pribat
发明人： Leonidas Karapiperis , Didier Pribat
IPC分类号： H01L33/00 , H01L21/20 , H01L21/205 , H01L21/329 , H01L29/205 , H01L29/47 , H01L29/872 , H01L29/93 , H01L47/02 , H01S5/00 , H01S5/026 , H01S5/20 , H01S5/22 , H01S5/30 , H01S5/40
CPC分类号： H01L29/66219 , H01L21/02381 , H01L21/02395 , H01L21/0245 , H01L21/02463 , H01L21/02546 , H01L21/02639 , H01L29/205 , H01S5/20 , H01S5/2203 , H01S5/2081 , H01S5/3072 , H01S5/3086 , Y10S148/026 , Y10S148/041
摘要： The invention pertains to the field of fabrication, by vapor phase deposition, of the thin layers of monocrystalline, polycrystalline or amorphous material on a substrate having an identical or different nature. The aim is to provide a method, enabling this structure to be made, that includes a modulation of both the composition and the doping, in a direction that is not perpendicular to the surface of the substrate, notably in a lateral way to obtain a planar technology. According to the invention, this thin layer is made by conformal epitaxy, using a crystalline seed in gas phase, between two confinement layers made of a distinct material in such a way that there can be neither nucleation nor deposition of semiconductive material on the surfaces of said confinement layers and wherein the variation of the gaseous mixture of said gas phase is controlled to obtain said modulation of the composition and/or of the doping of said thin film.
摘要翻译：本发明涉及通过气相沉积在具有相同或不同性质的基底上的单晶，多晶或非晶材料薄层的制造领域。目的是提供一种方法，使得能够在不垂直于衬底的表面的方向上形成包括组成和掺杂两者的调制的方法，特别是以横向方式获得平面技术。根据本发明，该薄层是通过保形外延法制成的，使用气相中的晶体种子，在由不同材料制成的两个约束层之间，使得半导体材料既不会成核也不能沉积在所述限制层并且其中控制所述气相的气体混合物的变化以获得所述薄膜的组成和/或掺杂的所述调制。

6. 发明授权

US4999314A Method for making an alternation of layers of monocrystalline semiconducting material and layers of insulating material 失效
标题翻译：制造单晶半导体材料层和绝缘材料层的交替方法
公开(公告)号：US4999314A
公开(公告)日：1991-03-12
申请号：US333016
申请日：1989-04-04
申请人： Didier Pribat , Leonidas Karapiperis
发明人： Didier Pribat , Leonidas Karapiperis
IPC分类号： H01L21/205 , H01L21/20 , H01L21/762 , H01L21/822 , H01L21/84
CPC分类号： H01L21/76248 , H01L21/02381 , H01L21/02543 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L21/02639 , H01L21/8221 , Y10S148/026 , Y10S148/05 , Y10S438/933
摘要： In a method for the fabrication of a layer of a monocrystalline semiconducting layer on a layer of insulating material, an epitaxial growth is achieved in a cavity closed by layers of dielectric material, using a seed of monocrystalline semiconducting material of a substrate. The growth takes place first of all, vertically, perpendicularly to the seed, and then horizontally in the plane of the cavity. This method thus enables a three-dimensional integration of semiconductor components.
摘要翻译：在用于在绝缘材料层上制造单晶半导体层的层的方法中，使用衬底的单晶半导体材料的种子在由介电材料层封闭的空腔中实现外延生长。生长首先垂直地垂直于种子，然后水平地在空腔的平面中发生。因此，该方法能够实现半导体部件的三维集成。

7. 发明授权

US4540452A Process for manufacturing a semi-conductor device of the type comprising at least one silicon layer deposited on an insulating substrate 失效
标题翻译：制造半导体器件的方法，该半导体器件包括沉积在绝缘衬底上的至少一个硅层
公开(公告)号：US4540452A
公开(公告)日：1985-09-10
申请号：US587641
申请日：1984-03-08
申请人： Michel Croset , Dominique Dieumegard , Didier Pribat
发明人： Michel Croset , Dominique Dieumegard , Didier Pribat
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L21/265 , H01L21/316 , H01L21/76
CPC分类号： H01L21/31654 , H01L21/26506 , Y10S148/003 , Y10S148/077 , Y10S148/117 , Y10S148/15 , Y10S438/967
摘要： The invention provides a process comprising a step for depositing at least one intrinsic or doped monocrystalline silicon layer on a substrate, also monocrystalline, followed by a step for forming a thin silica layer at the level of the original substrate-silicon interface. The silica layer is obtained by oxidation through the substrate, followed by a heat treatment step during which the monocrystalline silicon is oxidized by the implanted oxygen ions. The first approach may take place according to two variants: thermal or plasma oxidation of the silicon-substrate interface. Oxidation takes place during the return to ambient temperature of the stack of layers after the deposit has been made.
摘要翻译：本发明提供了一种方法，其包括在衬底上沉积至少一个固有或掺杂的单晶硅层的步骤，也是单晶的，随后在原始衬底 - 硅界面的水平上形成薄的二氧化硅层的步骤。二氧化硅层通过氧化通过基板获得，然后通过热处理步骤，其中单晶硅被注入的氧离子氧化。第一种方法可以根据两种变体进行：硅衬底界面的热或等离子体氧化。在沉积物制成之后，在叠层层的环境温度回升期间发生氧化。

8. 发明申请

US20050235906A1 Method for catalytic growth of nanotubes or nanofibers comprising a nisi alloy diffusion barrier 有权
标题翻译：包含nisi合金扩散阻挡层的纳米管或纳米纤维的催化生长方法
公开(公告)号：US20050235906A1
公开(公告)日：2005-10-27
申请号：US10497079
申请日：2002-12-03
申请人： Pierre Legagneux , Didier Pribat , Yannig Nedellec , Pierre Legasneux , Didier Pribat , Yannig Nedellec
发明人： Pierre Legagneux , Didier Pribat , Yannig Nedellec , Pierre Legasneux , Didier Pribat , Yannig Nedellec
IPC分类号： C01B31/02 , C30B11/00 , C30B11/12 , D01F9/127 , C30B23/00 , C30B25/00 , C30B28/12 , C30B29/58
CPC分类号： B82Y30/00 , B82Y40/00 , C01B32/162 , C30B11/00 , C30B11/12 , C30B29/36 , C30B29/52 , C30B29/605 , D01F9/127
摘要： The invention relates to a process for the growth of nanotubes or nanofibers on a substrate comprising at least an upper layer made of a first material, wherein: the formation, on the surface of the upper layer, of a barrier layer made of an alloy of the first material and of a second material, said alloy being stable at a first temperature; the formation of spots of catalyst that are made of the second material, on the surface of the alloy layer; and the growth of nanotubes or nanofibers at a second temperature below said first temperature. The alloy layer allows effective growth of nanotubes/nanofibers from catalyst spots on the surface of said alloy layer. This is because the alloy layer constitutes a diffusion barrier preventing the catalyst from diffusing into the growth substrate, which barrier is stable at the catalytic nanotube/nanofiber growth temperature.
摘要翻译：本发明涉及一种用于在基材上生长纳米管或纳米纤维的方法，该方法至少包括由第一材料制成的上层，其中：在上层的表面上形成由合金形成的阻挡层所述第一材料和第二材料，所述合金在第一温度下是稳定的; 在合金层的表面上形成由第二材料制成的催化剂斑点; 以及在低于所述第一温度的第二温度下纳米管或纳米纤维的生长。合金层允许纳米管/纳米纤维从所述合金层表面上的催化剂点有效生长。这是因为合金层构成阻止催化剂扩散到生长衬底中的扩散阻挡层，该阻挡层在催化纳米管/纳米纤维生长温度下是稳定的。

9. 发明授权

US08138046B2 Process for fabricating a nanowire-based vertical transistor structure 失效
标题翻译：用于制造基于纳米线的垂直晶体管结构的工艺
公开(公告)号：US08138046B2
公开(公告)日：2012-03-20
申请号：US12278173
申请日：2007-02-05
申请人： Didier Pribat , Costel-Sorin Cojocaru
发明人： Didier Pribat , Costel-Sorin Cojocaru
IPC分类号： H01L21/336
CPC分类号： H01L51/0512 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/7827 , H01L29/78642 , H01L51/0048
摘要： The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack of porous layers including a first insulating layer (20), a second conductive layer (12), providing the gate electrode function, and an upper insulating layer (13′) on the surface of the substrate covered with the first conductive layer (11) providing the drain or source electrode function. The porous layers having substantially stacked pores. The production of filaments made of a semiconductor material is inside some of the stacked pores of the porous layers. The production of the upper conductive layer provides the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.
摘要翻译：本发明涉及制造垂直晶体管结构的方法。在基板（10）上，提供源极或漏极功能的第一导电层（11）和提供漏极或源极功能的上导电层（17）。膜的制造包括一堆多孔层，包括提供栅电极功能的第一绝缘层（20），第二导电层（12）和覆盖在衬底的表面上的上绝缘层（13'）其中第一导电层（11）提供漏极或源极电极功能。多孔层具有基本上层叠的孔。由半导体材料制成的细丝的制造在多孔层的一些堆叠的孔内。上导电层的制造在填充有由半导体材料制成的细丝的多孔层的堆叠的表面上提供源极或漏极功能。

10. 发明授权

US07491269B2 Method for catalytic growth of nanotubes or nanofibers comprising a NiSi alloy diffusion barrier 有权
标题翻译：包含NiSi合金扩散阻挡层的纳米管或纳米纤维的催化生长方法
公开(公告)号：US07491269B2
公开(公告)日：2009-02-17
申请号：US10497079
申请日：2002-12-03
申请人： Pierre Legagneux , Didier Pribat , Yannig Nedellec
发明人： Pierre Legagneux , Didier Pribat , Yannig Nedellec
IPC分类号： C30B29/62
CPC分类号： B82Y30/00 , B82Y40/00 , C01B32/162 , C30B11/00 , C30B11/12 , C30B29/36 , C30B29/52 , C30B29/605 , D01F9/127
摘要： The invention relates to a process for the growth of nanotubes or nanofibers on a substrate comprising at least an upper layer made of a first material, wherein: the formation, on the surface of the upper layer, of a barrier layer made of an alloy of the first material and of a second material, said alloy being stable at a first temperature; the formation of spots of catalyst that are made of the second material, on the surface of the alloy layer; and the growth of nanotubes or nanofibers at a second temperature below said first temperature. The alloy layer allows effective growth of nanotubes/nanofibers from catalyst spots on the surface of said alloy layer. This is because the alloy layer constitutes a diffusion barrier preventing the catalyst from diffusing into the growth substrate, which barrier is stable at the catalytic nanotube/nanofiber growth temperature.
摘要翻译：本发明涉及一种用于在基材上生长纳米管或纳米纤维的方法，该方法至少包括由第一材料制成的上层，其中：在上层的表面上形成由合金形成的阻挡层所述第一材料和第二材料，所述合金在第一温度下是稳定的; 在合金层的表面上形成由第二材料制成的催化剂斑点; 以及在低于所述第一温度的第二温度下纳米管或纳米纤维的生长。合金层允许纳米管/纳米纤维从所述合金层表面上的催化剂点有效生长。这是因为合金层构成阻止催化剂扩散到生长衬底中的扩散阻挡层，该阻挡层在催化纳米管/纳米纤维生长温度下是稳定的。

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