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1. 发明授权

US5418935A Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received 失效
标题翻译：接收到在向其他驾驶员指示禁用指示之后通过延迟启动一个驾驶员来在公共总线上预防双重驱动事件的装置
公开(公告)号：US5418935A
公开(公告)日：1995-05-23
申请号：US167583
申请日：1993-12-14
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： G06F13/14 , G06F13/40 , G06F13/10 , G06F13/36
CPC分类号： G06F13/14 , G06F13/4077
摘要： In a digital data transfer system whereby a plurality of driver units are all connected to and share the same common system bus, there is provided control gating logic which will prevent the enablement of a subsequent driver for a fixed delay time until it is certain that the previous driver has been shut down. Due to switching time variations in driving units, a fixed delay time is set to function in a first driver that is beginning its data transmission to be sure that another driver which was previously transmitting data has been completely turned-off before the first driver gains access to the commonly shared bus. This ensures that no two drivers can simultaneously be driving data onto the system bus at the same time which would obviate the integrity of data transmitted.
摘要翻译：在数字数据传输系统中，多个驱动器单元都连接到并共享相同的公共系统总线，提供了控制门控逻辑，其将阻止后续驱动器实现固定的延迟时间，直到确定以前的司机已被关闭。由于驱动单元的切换时间变化，固定的延迟时间被设置为在正在开始其数据传输的第一驱动器中起作用，以确保在第一驱动器获得访问之前先前发送数据的另一驱动器已经完全关闭到共享公共汽车。这确保没有两个驱动程序可以同时将数据驱动到系统总线上，这将消除传输的数据的完整性。

2. 发明授权

US5459836A Inter-processor communication net 失效
标题翻译：处理器间通信网
公开(公告)号：US5459836A
公开(公告)日：1995-10-17
申请号：US970536
申请日：1992-11-02
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： G06F15/167 , G06F3/00 , G06F15/16
CPC分类号： G06F15/167
摘要： A message transfer system between multiple processors in a network. Each processor includes an interprocessor communications (IPC) hardware unit having an unique address count. An address count generator in a designated IPC hardware unit generates a sequence of binary count numbers such that when the generated count number matches the address of the IPC hardware unit, then that particular hardware unit and its associated processor are granted a time period of bus access for sending messages on the IPC network bus to other processors. Messages on the IPC network bus can be received by an IPC hardware unit at any time irrespective of the generated count number. Any sending processor that has bus access can concurrently provide multiple messages where each of the multiple messages is directed to each particular processor for reception. Thus one sender, with bus access, can communicate with multiple receivers during its transmission onto the IPC network bus connecting the processors.
摘要翻译：网络中多个处理器之间的消息传输系统。每个处理器包括具有唯一地址计数的处理器间通信（IPC）硬件单元。在指定的IPC硬件单元中的地址计数发生器产生二进制计数号序列，使得当生成的计数号与IPC硬件单元的地址匹配时，那个特定硬件单元及其相关处理器被授予总线访问时间段用于将IPC网络总线上的消息发送到其他处理器。 IPC网络总线上的消息可以由IPC硬件单元随时接收，而与生成的计数号无关。具有总线访问权的任何发送处理器可同时提供多个消息，其中多个消息中的每一个被定向到每个特定处理器用于接收。因此，一个具有总线访问权限的发送者可以在多个接收器传输到连接处理器的IPC网络总线上进行通信。

3. 发明授权

US5146596A Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests 失效
标题翻译：具有两级总线访问的多处理器多功能仲裁系统，包括优先级和正常请求
公开(公告)号：US5146596A
公开(公告)日：1992-09-08
申请号：US471904
申请日：1990-01-29
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： Arbitration and control circuitry for monitoring the two processors sharing a system bus to insure fair access to system resources and to sense error conditions which occur in order to hold access for the processor involved until the error condition is cleared. The arbitration circuitry provides for two levels of bus access requests where one level involves normal requests and a second level involves priority request which take precedence over normal requests.
摘要翻译：用于监视共享系统总线的两个处理器的仲裁和控制电路，以确保公平地访问系统资源，并感测发生的错误状况，以便保持所涉及的处理器的访问，直到错误状况被清除。仲裁电路提供两级总线访问请求，其中一级涉及正常请求，而第二级涉及优先于正常请求的优先级请求。

4. 发明授权

US5321814A System for optional module detection and reconfiguration 失效
标题翻译：可选模块检测和重新配置的系统
公开(公告)号：US5321814A
公开(公告)日：1994-06-14
申请号：US897610
申请日：1992-06-10
申请人： Saul Barajas , Leland E. Watson , Bruce E. Whittaker
发明人： Saul Barajas , Leland E. Watson , Bruce E. Whittaker
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4072
摘要： An automatic re-configurable computer system having a standard processor module and standard main memory and I/O control modules where each module is inter-connected to a common system bus. Automatic re-configuration occurs in the standard modules, when an optional module is connected onto the system bus, permitting inter-cooperation between the standard and optional modules to take place.
摘要翻译：一种具有标准处理器模块和标准主存储器和I / O控制模块的自动重新配置的计算机系统，其中每个模块与公共系统总线相互连接。自动重新配置发生在标准模块中，当可选模块连接到系统总线上时，允许标准模块和可选模块之间进行互操作。

5. 发明授权

US5117132A Flexible utilization of general flip-flops in programmable array logic 失效
标题翻译：一般触发器在可编程阵列逻辑中的灵活应用
公开(公告)号：US5117132A
公开(公告)日：1992-05-26
申请号：US652847
申请日：1991-02-08
申请人： Leland E. Watson , Saul Barajas , Bruce E. Whittaker
发明人： Leland E. Watson , Saul Barajas , Bruce E. Whittaker
IPC分类号： H03K19/177
CPC分类号： H03K19/17708
摘要： A programmable array logic unit (PAL) having a disconnected array of gates, inverters and D-Type flip-flops, is utilized by burning-in the interconnections, to enable the D flip-flops to function as J-K flip-flops and/or toggle flip-flops to enable flexibility in the functions available for utilization, by providing inputs for Direct Set, Direct Clear and Hold.
摘要翻译：具有断开的门阵列，反相器和D型触发器的可编程阵列逻辑单元（PAL）通过在互连中燃烧而被利用，以使D触发器用作JK触发器和/或通过提供直接设置，直接清除和保持的输入，可切换触发器以实现可用功能的灵活性。

6. 发明授权

US5086427A Clocked logic circuitry preventing double driving on shared data bus 失效
标题翻译：时钟逻辑电路防止共享数据总线上的双重驱动
公开(公告)号：US5086427A
公开(公告)日：1992-02-04
申请号：US506392
申请日：1990-04-09
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： H04J3/04 , H04L12/40
CPC分类号： H04J3/047
摘要： A system wherein multiple sources of data each have drivers for transmitting data to a common system bus. The drivers are each managed by individual enabling logic which is controlled by a flip-flop driven by a clock. Thus no driver can connect and drive data onto the bus until one clock period after the previously connected driver has been disabled and disconnected from the bus.
摘要翻译：一种系统，其中多个数据源具有用于将数据发送到公共系统总线的驱动器。驱动器各自由单个使能逻辑管理，该逻辑由时钟驱动的触发器控制。因此，在先前连接的驱动程序已被禁用并与总线断开连接之前，没有驱动程序可以连接和驱动数据到总线上。

7. 发明授权

US5537609A Mini cache operational module for enhancement to general cache 失效
标题翻译：迷你缓存操作模块，用于增强一般缓存
公开(公告)号：US5537609A
公开(公告)日：1996-07-16
申请号：US547260
申请日：1995-10-24
申请人： Bruce E. Whittaker , Leland E. Watson
发明人： Bruce E. Whittaker , Leland E. Watson
IPC分类号： G06F12/08 , G11C19/00
CPC分类号： G06F12/0897
摘要： A mini-cache module is added to a computer system to increase throughput or may also be added to enhance the functionality of a general cache memory unit. The mini-cache module refills and stores frequently used data words concurrently during processor operations and provides them to the processor, eliminating the need to access a system bus to main memory. A data queue storage stores a data block of words from main memory and makes them available to requests from the main processor (if the requested address matches an address register block in the mini-cache). If an address "hit" occurs, then the mini-cache will prevent any system bus request to main memory and additionally will monitor the system bus for any "Write" operations which might feasibly change the validity of data in the data storage block of the mini-cache. In this case the data stored in the mini-cache is invalidated and cannot be used by the processor.
摘要翻译：将微型缓存模块添加到计算机系统以增加吞吐量，或者也可以添加以将微型缓存模块添加到一般高速缓冲存储器单元的功能。微型缓存模块在处理器操作期间同时补充和存储频繁使用的数据字，并将其提供给处理器，从而无需访问主存储器的系统总线。数据队列存储器存储来自主存储器的字的数据块，并使其可用于来自主处理器的请求（如果所请求的地址与小型缓存中的地址寄存器块匹配）。如果发生地址“命中”，则微型缓存将防止对主存储器的任何系统总线请求，并且还将监视系统总线以进行任何“写入”操作，这可能可能改变数据存储块中的数据的有效性迷你缓存。在这种情况下，存储在微型缓存中的数据无效，处理器无法使用。

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