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1. 发明授权

US5939806A Drive motor for an electric vehicle 失效
标题翻译：驱动电动汽车电机
公开(公告)号：US5939806A
公开(公告)日：1999-08-17
申请号：US993039
申请日：1997-12-18
申请人： Ki-Nam Kim , Seung-Il Jang
发明人： Ki-Nam Kim , Seung-Il Jang
IPC分类号： H02K5/20 , H02K9/16
CPC分类号： H02K5/20 , Y02T10/641
摘要： A drive motor for an electric vehicle includes a cylindrical housing, a cylindrical stator disposed within the housing, a coil wound around the stator, a rotor disposed within the stator, and front and rear covers respectively coupled on front and rear ends of the housing. The housing includes a cylindrical coolant passage concentrically formed around the stator in the housing, and the front or rear cover includes a coolant inlet port through which coolant is fed to the coolant passage and a coolant outlet port through which coolant circulated the coolant passage is exhausted.
摘要翻译：一种用于电动车辆的驱动电动机包括圆柱形壳体，设置在壳体内的圆柱形定子，缠绕在定子上的线圈，设置在定子内的转子以及分别联接在壳体的前端和后端上的前后盖。壳体包括围绕壳体中的定子同心地形成的圆柱形冷却剂通道，并且前盖或后盖包括冷却剂入口，冷却剂通过所述冷却剂入口供给到冷却剂通道和冷却剂循环冷却剂通道的冷却剂出口。

2. 发明申请

US20130345464A1 I-AND II-TYPE CRYSTALS OF L-A-GLYCERYL PHOSPHORYL CHOLINE, AND METHOD FOR PREPARING SAME 有权
标题翻译： L-A-GLYCERYL PHOSPHORYL CHOLINE的I型和II型晶体及其制备方法
公开(公告)号：US20130345464A1
公开(公告)日：2013-12-26
申请号：US14003276
申请日：2012-02-22
申请人： Min-Keun Oh , Ki-Nam Kim , Ki-Hyeong Seo , Dae-Gil Kwon
发明人： Min-Keun Oh , Ki-Nam Kim , Ki-Hyeong Seo , Dae-Gil Kwon
IPC分类号： C07F9/09
CPC分类号： C07F9/091
摘要： The present invention relates to I- and II-type crystals of L-α-glyceryl phosphoryl choline, and to a method for preparing same. More particularly, the present invention relates to noble I- and II-type anhydride crystals of L-α-glyceryl phosphoryl choline, which have a higher purity than conventional liquid L-α-glyceryl phosphoryl choline, and one advantage of which is that formulations and dosages of pharmaceuticals are easily modified, and another advantage of which is that the hygroscopicity of the crystals are much lower than that of conventional polymorphic crystals, providing excellent stability during storage. The present invention also relates to a method for preparing the I- and II-type crystals of L-α-glyceryl phosphoryl choline.
摘要翻译：本发明涉及L-α-甘油磷酰胆碱的I型和II型晶体及其制备方法。更具体地，本发明涉及具有比常规液体L-α-甘油磷酰胆碱更高纯度的L-α-甘油磷酰胆碱的高级I型和II型酸酐晶体，其优点之一是制剂并且药物的剂量容易改性，其另一个优点是结晶的吸湿性远低于常规多晶型晶体的吸湿性，在储存期间提供极好的稳定性。本发明还涉及一种制备L-α-甘油磷酰胆碱的I型和II型晶体的方法。

3. 发明授权

US08026504B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08026504B2
公开(公告)日：2011-09-27
申请号：US12379814
申请日：2009-03-02
申请人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
发明人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , Y10S977/774
摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
摘要翻译：提供半导体器件及其形成方法。该方法包括制备半导体衬底。可以在半导体衬底上依次形成绝缘层。可以在绝缘层之间形成有源元件。可以在绝缘层中形成公共节点以电连接到有源元件。公共节点和有源元件可以二维重复地布置在半导体衬底上。

4. 发明授权

US07888667B2 Phase change memory device 失效
标题翻译：相变存储器件
公开(公告)号：US07888667B2
公开(公告)日：2011-02-15
申请号：US12008125
申请日：2008-01-09
申请人： Yoon-Jong Song , Se-Ho Lee , Ki-Nam Kim , Su-Youn Lee , Jae-Hyun Park
发明人： Yoon-Jong Song , Se-Ho Lee , Ki-Nam Kim , Su-Youn Lee , Jae-Hyun Park
IPC分类号： H01L47/00 , H01L21/00 , G11C11/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/1683 , Y10S438/90
摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.
摘要翻译：相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。加热电极设置在使基板穿过模具层的开口中。加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。填充绝缘图案填充由加热电极的侧壁围绕的空白区域。相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。相变材料图案接触加热电极的侧壁的顶表面。

5. 发明申请

US20100330752A1 Methods of Forming One Transistor DRAM Devices 有权
标题翻译：形成一个晶体管DRAM器件的方法
公开(公告)号：US20100330752A1
公开(公告)日：2010-12-30
申请号：US12842703
申请日：2010-07-23
申请人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
发明人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
IPC分类号： H01L21/322 , H01L21/336
CPC分类号： H01L27/10802 , H01L21/8221 , H01L27/0688 , H01L27/108 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
摘要翻译：一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

6. 发明申请

US20100002523A1 Flash Memory Devices that Utilize Age-Based Verify Voltages to Increase Data Reliability and Methods of Operating Same 有权
标题翻译：使用基于年龄的验证电压以提高数据可靠性的闪存设备和操作方法相同
公开(公告)号：US20100002523A1
公开(公告)日：2010-01-07
申请号：US12558717
申请日：2009-09-14
申请人： Ki-Tae Park , Yong-Seok Kim , Ki-Nam Kim , Yeong-Taek Lee
发明人： Ki-Tae Park , Yong-Seok Kim , Ki-Nam Kim , Yeong-Taek Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/344 , G11C16/3454
摘要： Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.
摘要翻译：公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。

7. 发明申请

US20090253257A1 METHODS OF FABRICATING MULTI-LAYER NONVOLATILE MEMORY DEVICES 有权
标题翻译：制造多层非易失性存储器件的方法
公开(公告)号：US20090253257A1
公开(公告)日：2009-10-08
申请号：US12478538
申请日：2009-06-04
申请人： Young-Chul Jang , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
发明人： Young-Chul Jang , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
IPC分类号： H01L21/8246 , H01L21/4763 , H01L21/3205
CPC分类号： H01L27/105 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.
摘要翻译：非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

8. 发明申请

US20090218558A1 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20090218558A1
公开(公告)日：2009-09-03
申请号：US12379814
申请日：2009-03-02
申请人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
发明人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , Y10S977/774
摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
摘要翻译：提供半导体器件及其形成方法。该方法包括制备半导体衬底。可以在半导体衬底上依次形成绝缘层。可以在绝缘层之间形成有源元件。可以在绝缘层中形成公共节点以电连接到有源元件。公共节点和有源元件可以二维重复地布置在半导体衬底上。

9. 发明申请

US20090207666A1 Methods of Restoring Data in Flash Memory Devices and Related Flash Memory Device Memory Systems 审中-公开
标题翻译：恢复闪存设备和相关闪存设备内存系统中数据的方法
公开(公告)号：US20090207666A1
公开(公告)日：2009-08-20
申请号：US12428062
申请日：2009-04-22
申请人： Ki-Tae Park , Ki-Nam Kim , Yeong-Taek Lee
发明人： Ki-Tae Park , Ki-Nam Kim , Yeong-Taek Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/349 , G11C16/3495
摘要： Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.
摘要翻译：包括闪速存储器装置和用于控制闪速存储器件的存储器控制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

10. 发明授权

US07518909B2 Non-volatile memory device adapted to reduce coupling effect between storage elements and related methods 有权
标题翻译：适用于减少存储元件之间的耦合效应和相关方法的非易失性存储器件
公开(公告)号：US07518909B2
公开(公告)日：2009-04-14
申请号：US11606908
申请日：2006-12-01
申请人： Ki-Tae Park , Ki-Nam Kim , Yeong-Taek Lee
发明人： Ki-Tae Park , Ki-Nam Kim , Yeong-Taek Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12 , G11C16/3427 , G11C2211/5621 , G11C2211/5642
摘要： A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.
摘要翻译：非挥发性半导体存储器件包括第一和第二子存储器阵列和布置在第一和第二子存储器阵列之间的捆扎线。通过同时向连接到第一子存储器阵列内的存储单元的奇偶位线施加编程电压来执行第一子存储器阵列的编程操作。

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