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1. 发明申请

US20080198945A1 REDUCED EMI DEVICE AND METHOD THEREOF 审中-公开
标题翻译：降低EMI器件及其方法
公开(公告)号：US20080198945A1
公开(公告)日：2008-08-21
申请号：US12062357
申请日：2008-04-03
申请人： Kenneth W. Egan , Gregory T. Chandler , Jitendra K. Budwal , James J. Remedi , Ted Beck , Stephen J. Sheafor
发明人： Kenneth W. Egan , Gregory T. Chandler , Jitendra K. Budwal , James J. Remedi , Ted Beck , Stephen J. Sheafor
IPC分类号： H04L25/03 , H04L25/49
CPC分类号： H04B15/04 , G06F1/10 , G06F1/189 , H04B1/707
摘要： A method and system are disclosed for spreading the power associated with digital signals being transmitted to reduce electromagnetic interference (EMI) emissions by receiving, via a first transmission line, a first power spread signal representative a first digital signal modified using a first power spreading digital noise signal, modifying the power spread signal using a second power spreading digital noise signal substantially similar to the first power spreading digital noise signal to generate a second digital signal substantially similar to the first digital signal, modifying the second digital signal using a third power spreading digital noise signal to generate a second power spread signal and providing the second power spread signal for output to a second transmission line.
摘要翻译：公开了一种方法和系统，用于通过经由第一传输线接收代表使用第一功率扩展数字（10）修改的第一数字信号的第一功率扩展信号来扩展与所传输的数字信号相关联的功率以减少电磁干扰（EMI）噪声信号，使用基本上类似于第一功率扩展数字噪声信号的第二功率扩展数字噪声信号修改功率扩展信号，以产生基本上类似于第一数字信号的第二数字信号，使用第三功率扩展修改第二数字信号数字噪声信号以产生第二功率扩展信号，并提供第二功率扩展信号以输出到第二传输线。

2. 发明授权

US07386028B2 Reduced EMI device and method thereof 失效
标题翻译：降低EMI装置及其方法
公开(公告)号：US07386028B2
公开(公告)日：2008-06-10
申请号：US11003986
申请日：2004-12-03
申请人： Kenneth W. Egan , Gregory T. Chandler , Jitendra K. Budwal , James J. Remedi , Ted Beck , Stephen J. Sheafor
发明人： Kenneth W. Egan , Gregory T. Chandler , Jitendra K. Budwal , James J. Remedi , Ted Beck , Stephen J. Sheafor
IPC分类号： H04B1/69 , H04B3/00
CPC分类号： H04B15/04 , G06F1/10 , G06F1/189 , H04B1/707
摘要： A method and system is disclosed for spreading the power associated with digital signals being transmitted to reduce electromagnetic interference (EMI) emissions by receiving, via a first transmission line, a first power spread signal representative a first digital signal modified using a first power spreading digital noise signal, modifying the power spread signal using a second power spreading digital noise signal substantially similar to the first power spreading digital noise signal to generate a second digital signal substantially similar to the first digital signal, modifying the second digital signal using a third power spreading digital noise signal to generate a second power spread signal and providing the second power spread signal for output to a second transmission line.
摘要翻译：公开了一种方法和系统，用于通过经由第一传输线接收代表使用第一功率扩展数字（DVI）修改的第一数字信号的第一功率扩展信号来扩展与所传输的数字信号相关联的功率以减少电磁干扰（EMI）噪声信号，使用基本上类似于第一功率扩展数字噪声信号的第二功率扩展数字噪声信号修改功率扩展信号，以产生基本上类似于第一数字信号的第二数字信号，使用第三功率扩展修改第二数字信号数字噪声信号以产生第二功率扩展信号，并提供第二功率扩展信号以输出到第二传输线。

3. 发明授权

US4176287A Versatile CMOS decoder 失效
标题翻译：多功能CMOS解码器
公开(公告)号：US4176287A
公开(公告)日：1979-11-27
申请号：US896071
申请日：1978-04-13
申请人： James J. Remedi
发明人： James J. Remedi
IPC分类号： H03M7/20 , H03M13/51 , H03K17/60 , H03K5/18 , H03K13/00
CPC分类号： H03M13/51 , H03M7/20
摘要： A CMOS decoder capable of providing a one of n, a two of n, or a three of n decoded output, where n is equal to the number of outputs of the decoder and is a function of the number of bits in a digital signal to be decoded. A first plurality of transistors are used to precharge each of the decoder's outputs to a first voltage potential. A second plurality of transistors are placed in series between the first node and each of the outputs. The second plurality of transistors are controlled by the coded digital signal that is being decoded. The number of decoded outputs can be varied by connecting some of the outputs to some of the transistors of the second plurality of transistors or by connecting others of the outputs to junctions formed by the series placed transistors. In a preferred embodiment, a pair of back-to-back inverters are connected to each of the outputs to provide a static decoder.
摘要翻译：能够提供n，n中的n个或n个解码输出中的三个的CMOS解码器，其中n等于解码器的输出数，并且是数字信号中的位数的函数被解码。使用第一多个晶体管来将每个解码器的输出预充电到第一电压电位。在第一节点和每个输出之间串联放置第二多个晶体管。第二多个晶体管由被解码的编码数字信号控制。可以通过将一些输出连接到第二多个晶体管的一些晶体管或通过将其他输出连接到由串联放置的晶体管形成的结而改变解码输出的数量。在优选实施例中，一对背对背反相器连接到每个输出以提供静态解码器。

4. 发明授权

US4145759A Virtual power supply ROM 失效
标题翻译：虚拟电源ROM
公开(公告)号：US4145759A
公开(公告)日：1979-03-20
申请号：US895848
申请日：1978-04-13
申请人： James J. Remedi
发明人： James J. Remedi
IPC分类号： G11C17/00 , G11C17/12 , G11C17/18 , G11C11/40
CPC分类号： G11C17/126
摘要： A read-only-memory is provided on a semiconductor chip having a reduced number of power supply lines. The memory has a plurality of storage cells arranged in an array. Vertical lines define columns of the memory. Every other vertical line is coupled to a first node. The first node is controllably coupled to a first voltage potential to controllably precharge the first node. The vertical lines not connected to the first node are connected to an output node. P channel field effect transistors are used to couple the vertical lines to the first node and to the output node. A plurality of N-channel field effect transistors controllably couple the vertical lines to a second voltage potential. A vertical line on one side of the column of memory cells is used to provide a precharge voltage to the cell while a vertical line on the other side of the column of memory cells is used to conduct stored information from the cell to the output node. The vertical lines are shared by adjacent columns of memory cells thereby reducing the number of power supply lines.
摘要翻译：在具有减少数量的电源线的半导体芯片上提供只读存储器。存储器具有以阵列布置的多个存储单元。垂直线定义存储器的列。每隔一条垂直线耦合到第一个节点。第一节点被可控地耦合到第一电压电位以可控制地预充电第一节点。未连接到第一个节点的垂直线连接到输出节点。 P沟道场效应晶体管用于将垂直线耦合到第一节点和输出节点。多个N沟道场效应晶体管可控制地将垂直线耦合到第二电压电位。存储单元列的一侧上的垂直线用于向单元提供预充电电压，而存储单元列的另一侧上的垂直线用于将存储的信息从单元传送到输出节点。垂直线由存储器单元的相邻列共享，从而减少电源线的数量。

5. 发明授权

US4758945A Method for reducing power consumed by a static microprocessor 失效
标题翻译：降低静态微处理器功耗的方法
公开(公告)号：US4758945A
公开(公告)日：1988-07-19
申请号：US065292
申请日：1979-08-09
申请人： James J. Remedi
发明人： James J. Remedi
IPC分类号： G06F1/32 , G06F1/04
CPC分类号： G06F9/30083 , G06F1/3228
摘要： In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.
摘要翻译：响应于软件指令，通过禁止产生时钟脉冲，将静态微处理器置于低电流模式。提供了当STOP指令被解码时禁用主振荡器的装置。提供了在WAIT指令被解码而禁用主振荡器时抑制时钟脉冲的附加装置。接收到复位或中断信号后，再次使能时钟脉冲生成。

6. 发明授权

US4511914A Power bus routing for providing noise isolation in gate arrays 失效
标题翻译：电源总线路由，用于在门阵列中提供噪声隔离
公开(公告)号：US4511914A
公开(公告)日：1985-04-16
申请号：US394239
申请日：1982-07-01
申请人： James J. Remedi , Don G. Reid , Lynette Ure
发明人： James J. Remedi , Don G. Reid , Lynette Ure
IPC分类号： H01L21/822 , H01L21/82 , H01L23/48 , H01L23/52 , H01L25/07 , H01L25/11 , H01L27/04 , H01L27/10 , H01L27/118 , H01L27/15 , H01L27/02
CPC分类号： H01L23/52 , H01L25/071 , H01L25/112 , H01L2924/0002
摘要： A gate array which has power bus routing for increasing current availability to a plurality of transistor cells is provided. The gate array also has separate power busses for input/internal logic and output circuits. The gate array comprises n columns of transistor cells with two power busses extending substantially along each column to power the cells. Input/internal logic power busses and separate output power busses extend around the perimeter of the columns of transistor cells. At least one power strip for increasing current availability to the transistor cells is routed across the transistor cells substantially perpendicular to the n columns and is connected to both the power busses of each column and to the input/internal logic power busses.
摘要翻译：提供了具有用于增加多个晶体管单元的电流可用性的电源总线布线的门阵列。门阵列还具有用于输入/内部逻辑和输出电路的单独的功率总线。门阵列包括n列晶体管单元，其中两个功率总线基本上沿每列延伸以对单元供电。输入/内部逻辑电源总线和单独的输出功率总线围绕晶体管单元的列的周边延伸。用于提高晶体管单元的电流可用性的至少一个电源条被跨过基本上垂直于n列的晶体管单元，并且连接到每列的功率总线和输入/内部逻辑功率总线。

7. 发明授权

US4300065A Power on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US4300065A
公开(公告)日：1981-11-10
申请号：US54092
申请日：1979-07-02
申请人： James J. Remedi , Alan K. Peterson
发明人： James J. Remedi , Alan K. Peterson
IPC分类号： H03K17/22 , H03K17/687
CPC分类号： H03K17/223
摘要： A CMOS power on reset circuit is provided which operates with low power supply voltages and yet uses a minimum amount of DC power. The circuit includes a threshold detector which provides an output when the power supply voltage exceeds the transistor threshold voltage by approximately half a volt. A capacitor is connected to the positive power supply terminal to avoid having a narrow output pulse when the power supply rises at a low rate. An output buffer/inverter can be used to provide a better output pulse and to provide a desired output polarity.
摘要翻译：提供CMOS功率上电复位电路，其以低电源电压工作，并且使用最小量的DC电力。电路包括阈值检测器，当电源电压超过晶体管阈值电压大约半伏时提供输出。电容器连接到正电源端子，以避免当电源以低速上升时具有窄的输出脉冲。可以使用输出缓冲器/反相器来提供更好的输出脉冲并提供期望的输出极性。

8. 发明授权

US4165504A CMOS Decoder 失效
标题翻译： CMOS解码器
公开(公告)号：US4165504A
公开(公告)日：1979-08-21
申请号：US895849
申请日：1978-04-13
申请人： James J. Remedi
发明人： James J. Remedi
IPC分类号： H03M7/00 , H04Q3/00
CPC分类号： H03M7/005
摘要： A CMOS digital decoder has a plurality of circuits having first and second output nodes. A first transistor is used to precharge the first output node and a second transistor is used to precharge the second output node. A third transistor responsive to an enable signal is used to enable the decoder. A fourth transistor is coupled between the third transistor and the first output node and a fifth transistor is coupled between the third transistor and the second output node. A plurality of transistors can be in series between the fourth transistor and the third transistor, or the plurality of transistors can be in parallel between the first and second output nodes depending upon the type of decoder output desired. The decoder can be made a static decoder by coupling a pair of back-to-back inverters to each of the output nodes.
摘要翻译： CMOS数字解码器具有多个具有第一和第二输出节点的电路。第一晶体管用于对第一输出节点进行预充电，第二晶体管用于对第二输出节点进行预充电。响应于使能信号的第三晶体管用于使能解码器。第四晶体管耦合在第三晶体管和第一输出节点之间，第五晶体管耦合在第三晶体管和第二输出节点之间。多个晶体管可以串联在第四晶体管和第三晶体管之间，或者多个晶体管可以在第一和第二输出节点之间并联，这取决于所需的解码器输出的类型。通过将一对背对背反相器耦合到每个输出节点，可以将解码器制成静态解码器。

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