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1. 发明授权

US6022792A Semiconductor dicing and assembling method 失效
标题翻译：半导体切割和组装方法
公开(公告)号：US6022792A
公开(公告)日：2000-02-08
申请号：US815907
申请日：1997-03-12
申请人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
发明人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
IPC分类号： H01L21/301 , H01L21/78 , H01L23/485 , H01L23/532
CPC分类号： H01L24/05 , H01L21/78 , H01L23/53228 , H01L23/53238 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05022 , H01L2224/05073 , H01L2224/05166 , H01L2224/05552 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05572 , H01L2224/05599 , H01L2224/05624 , H01L2224/06051 , H01L2224/13017 , H01L2224/13027 , H01L2224/13099 , H01L2224/13144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/75252 , H01L2224/85201 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025
摘要： To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
摘要翻译：为了减小芯片的面积，提高制造效率，降低诸如具有多个输出焊盘的驱动器集成电路等半导体装置以及诸如电子时钟之类的电子电路装置的成本。在驱动晶体管或连接到其的逻辑电路上分别布置有两个重叠的输出焊盘。此外，不仅铝互连而且凸起电极或阻挡金属用于半导体器件的互连。在将半导体集成电路以面朝下的方式电粘接到印刷电路板的情况下，设置在半导体集成电路上的焊料凸块和印刷电路板的互连直接连接，从而实现电气连接。在这种情况下，作为半导体集成电路的外部连接端子的突起电极层叠在晶体管上。

2. 发明授权

US06492692B1 Semiconductor integrated circuit and manufacturing method therefore 有权
标题翻译：因此，半导体集成电路和制造方法
公开(公告)号：US06492692B1
公开(公告)日：2002-12-10
申请号：US09407382
申请日：1999-09-28
申请人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
发明人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
IPC分类号： H01L2972
CPC分类号： H01L24/05 , H01L21/78 , H01L23/53228 , H01L23/53238 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05017 , H01L2224/05022 , H01L2224/05073 , H01L2224/05166 , H01L2224/05552 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05572 , H01L2224/05599 , H01L2224/05624 , H01L2224/06051 , H01L2224/13017 , H01L2224/13027 , H01L2224/13099 , H01L2224/13144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/75252 , H01L2224/85201 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
摘要翻译：为了减小芯片的面积，提高制造效率，降低诸如具有多个输出焊盘的驱动器集成电路等半导体装置以及诸如电子时钟之类的电子电路装置的成本。在驱动晶体管或连接到其的逻辑电路上分别布置有两个重叠的输出焊盘。此外，不仅铝互连而且凸起电极或阻挡金属用于半导体器件的互连。在半导体集成电路以面朝下的方式电粘接到印刷电路板的情况下，设置在半导体集成电路上的焊料凸块和印刷电路板的互连直接连接，从而实现电气连接。在这种情况下，作为半导体集成电路的外部连接端子的突起电极层叠在晶体管上。

3. 发明授权

US06222235B1 Small geometry high voltage semiconductor device 失效
标题翻译：小几何高压半导体器件
公开(公告)号：US06222235B1
公开(公告)日：2001-04-24
申请号：US08677541
申请日：1996-07-10
申请人： Yoshikazu Kojima , Kazutoshi Ishii , Masaaki Kamiya , Yasuhiro Moya
发明人： Yoshikazu Kojima , Kazutoshi Ishii , Masaaki Kamiya , Yasuhiro Moya
IPC分类号： H01L2362
CPC分类号： H01L29/7834 , H01L27/0266 , H01L27/092 , H01L29/0847 , H01L29/105 , H01L29/42364 , H01L29/42368 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.
摘要翻译：在其输出部分中包括多个高电压驱动晶体管的半导体器件通过将静电保护晶体管与连接到输出焊盘的高电压驱动晶体管并联连接来提高静电耐受电压。使静电保护晶体管的漏极耐受电压低于高电压驱动晶体管的漏极耐受电压。此外，静电保护晶体管的沟道长度变短，以实现静电保护晶体管的高效双极性操作。

4. 发明授权

US06747319B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06747319B2
公开(公告)日：2004-06-08
申请号：US09803624
申请日：2001-03-09
申请人： Yoshikazu Kojima , Kazutoshi Ishii , Masaaki Kamiya , Yasuhiro Moya
发明人： Yoshikazu Kojima , Kazutoshi Ishii , Masaaki Kamiya , Yasuhiro Moya
IPC分类号： H01L2976
CPC分类号： H01L29/7834 , H01L27/0266 , H01L27/092 , H01L29/0847 , H01L29/105 , H01L29/42364 , H01L29/42368 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.
摘要翻译：在其输出部分中包括多个高电压驱动晶体管的半导体器件通过将静电保护晶体管与连接到输出焊盘的高电压驱动晶体管并联连接来提高静电耐受电压。使静电保护晶体管的漏极耐受电压低于高电压驱动晶体管的漏极耐受电压。此外，静电保护晶体管的沟道长度变短，以实现静电保护晶体管的高效双极性操作。

5. 发明授权

US06359639B1 Thermal head driving integrated circuit 有权
标题翻译：热敏头驱动集成电路
公开(公告)号：US06359639B1
公开(公告)日：2002-03-19
申请号：US09428901
申请日：1999-10-28
申请人： Tatsuya Kitta , Yoshihide Kanakubo , Yasuhiro Moya , Kazutoshi Ishii , Sumitaka Gotou
发明人： Tatsuya Kitta , Yoshihide Kanakubo , Yasuhiro Moya , Kazutoshi Ishii , Sumitaka Gotou
IPC分类号： B41J2345
CPC分类号： B41J2/355
摘要： A thermal head driving integrated circuit capable of preventing the lowering of data transfer speed, and in which the number of bonding pads can be reduced as well as current consumption has a driver circuit in which at least two shift registers are series-arranged in front and rear stages to sequentially transfer print data in a serial signal manner to be read out in a batch mode to drive a plurality of heating resistive elements. A switch circuit is interposed between an output terminal of the front-staged shift register and an input terminal of the rear-staged shift register to selectively connect and disconnect the two shift registers.
摘要翻译：能够防止数据传送速度降低的热敏头驱动集成电路，其中可以减少接合焊盘的数量以及电流消耗，具有驱动电路，其中至少两个移位寄存器串联排列在前面，后级以串行信号方式顺序传送打印数据，以便以分批模式读出以驱动多个加热电阻元件。开关电路插在前级移位寄存器的输出端子和后级移位寄存器的输入端子之间，以选择性地连接和断开两个移位寄存器。

6. 发明授权

US6134136A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US6134136A
公开(公告)日：2000-10-17
申请号：US236896
申请日：1999-01-26
申请人： Kazutoshi Ishii , Sumitaka Gotou , Yasuhiro Moya , Yoshihide Kanakubo , Tatuya Kitta
发明人： Kazutoshi Ishii , Sumitaka Gotou , Yasuhiro Moya , Yoshihide Kanakubo , Tatuya Kitta
IPC分类号： B41J2/345 , G11C5/00 , H01L21/822 , H01L27/04 , G11C5/02
CPC分类号： G09G3/3685 , B41J2/3359 , G09G2330/04 , H01L2924/0002
摘要： Reducing the chip area while improving the manufacturing efficiency as well as reducing costs in a semiconductor integrated circuit device such as a thermal head driver IC. A plurality of terminal electrodes were provided within an external data input/output circuit with an input terminal and output terminal being electrically connected to each other. In addition, an input/output protection circuit was provided to a respective one of such plurality of terminal electrodes with the input terminal and output terminal electrically connected together.
摘要翻译：在提高制造效率的同时降低芯片面积并降低诸如热敏头驱动器IC的半导体集成电路器件的成本。多个端子电极设置在外部数据输入/输出电路内，输入端子和输出端子彼此电连接。此外，输入/输出保护电路被提供给这些多个端子电极中的相应一个，输入端子和输出端子电连接在一起。

7. 发明授权

US06346960B1 Thermal head driving integrated circuit 有权
标题翻译：热敏头驱动集成电路
公开(公告)号：US06346960B1
公开(公告)日：2002-02-12
申请号：US09404936
申请日：1999-09-23
申请人： Yoshihide Kanakubo , Yasuhiro Moya , Tatsuya Kitta , Kazutoshi Ishii , Sumitaka Goto
发明人： Yoshihide Kanakubo , Yasuhiro Moya , Tatsuya Kitta , Kazutoshi Ishii , Sumitaka Goto
IPC分类号： B41J2345
CPC分类号： B41J2/355
摘要： A thermal head driving integrated circuit may be used to perform an “n” color or “n” gradation printing operation with a simplified circuit having a reduced size by employing a single delay element connected to a plurality of resistive heating elements. The integrated circuit has a plurality of drive units each for driving a respective one of the heating elements and each having a drive transistor for driving a respective heating element, one or more delay elements, the number of delay elements being less than “n”, for supplying delayed print data to the drive transistor, a print data storing unit for storing the print data of each of the “n” types, and a print data supplying unit for supplying print data stored in the print data storing unit to the “n” delay elements.
摘要翻译：可以使用热敏头驱动集成电路，通过采用连接到多个电阻加热元件的单个延迟元件，通过具有减小的尺寸的简化电路来执行“n”种颜色或“n”级别打印操作。集成电路具有多个驱动单元，每个驱动单元用于驱动相应的一个加热元件，并且每个驱动单元具有用于驱动相应加热元件的驱动晶体管，一个或多个延迟元件，延迟元件的数量小于“n” 用于将延迟的打印数据提供给驱动晶体管;打印数据存储单元，用于存储每个“n”类型的打印数据，以及打印数据提供单元，用于将存储在打印数据存储单元中的打印数据提供给“n” “延迟元素

8. 发明授权

US6107128A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US6107128A
公开(公告)日：2000-08-22
申请号：US324693
申请日：1999-06-02
申请人： Kazutoshi Ishii , Sumitaka Gotou , Yasuhiro Moya , Tatsuya Kitta , Yoshihide Kanakubo
发明人： Kazutoshi Ishii , Sumitaka Gotou , Yasuhiro Moya , Tatsuya Kitta , Yoshihide Kanakubo
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0925 , H01L21/823857
摘要： Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided in the vicinity of the surface of a semiconductor substrate through a gate insulating film, a second conductive type heavily doped impurity region is provided in a region adjacent to a part of the gate electrode through a part of the gate insulating film and a part of a thick oxide film, another second conductive type heavily doped impurity region is provided in a region adjacent to an opposite part of the gate electrode opposing the part of the gate electrode through the part of the gate insulating film and a part of another thick oxide film, and a first conductive type heavily doped impurity region for device isolation is provided so as to surround the gate electrode and the second conductive type heavily doped impurity regions.
摘要翻译：由于能够以较少数量的制造工艺形成场效应MOS晶体管，所以能够以低成本实现半导体集成电路器件。半导体器件具有其中通过栅极绝缘膜在半导体衬底的表面附近设置栅电极的结构，在与栅电极的一部分相邻的区域中设置第二导电型重掺杂杂质区通过栅极绝缘膜的一部分和厚氧化物膜的一部分，另一个第二导电型重掺杂杂质区设置在与栅电极的与栅电极的一部分相对的相对部分附近的区域中，设置栅绝缘膜和另一厚氧化膜的一部分，以及用于器件隔离的第一导电型重掺杂杂质区域，以围绕栅电极和第二导电型重掺杂杂质区。

9. 发明授权

US06469405B1 Constant-current output driver with reduced over-shoot 有权
标题翻译：恒流输出驱动器减少了超拍
公开(公告)号：US06469405B1
公开(公告)日：2002-10-22
申请号：US09493773
申请日：2000-01-28
申请人： Yasuhiro Moya , Tatsuya Kitta , Yoshihide Kanakubo , Tadao Akamine
发明人： Yasuhiro Moya , Tatsuya Kitta , Yoshihide Kanakubo , Tadao Akamine
IPC分类号： H01H3500
CPC分类号： G09G3/3283 , G09G3/3216 , G09G5/02 , G09G2300/06 , G09G2310/0297 , G09G2320/041 , G09G2330/028 , H04N5/70 , H04N9/30 , H05B33/0896 , Y10T307/858
摘要： A constant-current FET functions as a constant current element by application of a constant voltage to the gate thereof. A first switch FET is disposed between the constant-current FET and a power supply without another switching element being disposed between the constant current FET and an output terminal. A second switch FET that performs an on/off operation in association with an on/off operation performed by the first switch FET is connected between the output terminal and ground.
摘要翻译：恒流FET通过向其栅极施加恒定电压而用作恒流元件。第一开关FET设置在恒流FET和电源之间，而没有另外的开关元件设置在恒流FET和输出端之间。与第一开关FET执行的接通/断开操作相关联地执行导通/截止操作的第二开关FET连接在输出端子和地之间。

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