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1. 发明授权

US07416976B2 Method of forming contacts using auxiliary structures 有权
标题翻译：使用辅助结构形成触点的方法
公开(公告)号：US07416976B2
公开(公告)日：2008-08-26
申请号：US11217122
申请日：2005-08-31
申请人： Josef Willer , Patrick Haibach , Christoph Andreas Kleint , Nicolas Nagel
发明人： Josef Willer , Patrick Haibach , Christoph Andreas Kleint , Nicolas Nagel
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.
摘要翻译：半导体产品包括具有基板表面的基板。多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。在字线之间提供多个导电接触结构。该产品还包括多个填充结构。每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。两个相应的接触结构在第一方向上彼此间隔一定距离。在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

2. 发明申请

US20070048993A1 Semiconductor product and method for forming a semiconductor product 有权
标题翻译：用于形成半导体产品的半导体产品和方法
公开(公告)号：US20070048993A1
公开(公告)日：2007-03-01
申请号：US11217122
申请日：2005-08-31
申请人： Josef Willer , Patrick Haibach , Christoph Kleint , Nicolas Nagel
发明人： Josef Willer , Patrick Haibach , Christoph Kleint , Nicolas Nagel
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.
摘要翻译：半导体产品包括具有基板表面的基板。多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。在字线之间提供多个导电接触结构。该产品还包括多个填充结构。每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。两个相应的接触结构在第一方向上彼此间隔一定距离。在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

3. 发明申请

US20080237738A1 Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell arrangement; memory module 审中-公开
标题翻译：集成电路，电池，电池布置，集成电路的制造方法，电池装置的制造方法。内存模块
公开(公告)号：US20080237738A1
公开(公告)日：2008-10-02
申请号：US11728970
申请日：2007-03-27
申请人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
发明人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/743 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： The present invention relates generally to integrated circuits, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module. In an embodiment of the invention, an integrated circuit having a cell is provided. The cell includes a first source/drain region, a second source/drain region, an active region between the first source/drain region and the second source/drain region, a gate insulating region disposed above the active region, a gate region disposed above the gate insulating region, and at least one metal structure below the first source/drain region or the second source/drain region.
摘要翻译：本发明一般涉及集成电路，单元，单元布置，集成电路的制造方法，单元布置的制造方法和存储器模块。在本发明的实施例中，提供了具有单元的集成电路。电池包括第一源极/漏极区域，第二源极/漏极区域，第一源极/漏极区域和第二源极/漏极区域之间的有源区域，设置在有源区域上方的栅极绝缘区域，栅极绝缘区域以及在第一源极/漏极区域或第二源极/漏极区域下方的至少一个金属结构。

4. 发明申请

US20080009115A1 Method of manufacturing at least one semiconductor component and memory cells 有权
标题翻译：制造至少一个半导体部件和存储单元的方法
公开(公告)号：US20080009115A1
公开(公告)日：2008-01-10
申请号：US11483968
申请日：2006-07-10
申请人： Josef Willer , Nicolas Nagel
发明人： Josef Willer , Nicolas Nagel
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/792
摘要： A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.
摘要翻译：公开了制造至少一个NAND耦合的半导体部件的方法。在半导体衬底上或上方形成层结构。图案化层结构以暴露待掺杂的至少一个区域。曝光区域被掺杂并退火。图案化层结构至少部分地被去除。在去除图案层结构的区域中形成更换材料，从而形成至少一个NAND耦合的半导体部件。

5. 发明授权

US07838921B2 Memory cell arrangements 有权
标题翻译：存储单元布置
公开(公告)号：US07838921B2
公开(公告)日：2010-11-23
申请号：US11526149
申请日：2006-09-22
申请人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
发明人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.
摘要翻译：存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管晶体管，其中至少有一些是存储单元。电介质材料在第一存储单元串和第二存储单元串之间和之上。源极/漏极线沟槽限定在电介质材料中。源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。导电填充材料设置在源极/漏极线槽中。电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

6. 发明申请

US20080080226A1 Memory system and method of operating the memory system 审中-公开
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US20080080226A1
公开(公告)日：2008-04-03
申请号：US11526850
申请日：2006-09-25
申请人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
发明人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/5614 , G11C7/1006 , G11C7/22 , G11C11/16 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2207/107 , G11C2211/5641
摘要： A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.
摘要翻译：存储器系统包括多个电阻存储单元区域，至少包括第一电阻存储单元区域和第二电阻存储单元区域，第一电阻存储单元区域形成有多个电阻存储单元，以第一数据存储速度存储数据形成有以低于第一数据存储速度的第二数据存储速度存储数据的多个电阻性存储单元形成的第二电阻性存储单元区域，以及控制器，用于控制多个电阻性存储单元区域之间的数据传输。

7. 发明申请

US20070231991A1 Semiconductor memory device and method of operating a semiconductor memory device 审中-公开
标题翻译：半导体存储器件和操作半导体存储器件的方法
公开(公告)号：US20070231991A1
公开(公告)日：2007-10-04
申请号：US11396398
申请日：2006-03-31
申请人： Josef Willer , Nicolas Nagel , Thomas Mikolajick , Karl-Heinz Kuesters
发明人： Josef Willer , Nicolas Nagel , Thomas Mikolajick , Karl-Heinz Kuesters
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/14 , G11C16/16
摘要： A semiconductor memory device includes a channel region, a gate electrode adjacent the channel region, and a charge-trapping layer between the channel region and the gate electrode. A voltage is applied between the gate electrode and the channel region to cause a first current of a first kind of charge carriers from the channel region to move into the charge-trapping layer and to cause a second current of a second kind of charge carriers from the gate electrode to move into the charge-trapping layer, until the value of the second current is at least half the amount of the first current value.
摘要翻译：半导体存储器件包括沟道区，与沟道区相邻的栅电极以及沟道区和栅电极之间的电荷俘获层。在栅极电极和沟道区域之间施加电压，使来自沟道区域的第一种电荷载流子的第一电流移动到电荷俘获层中，并引起第二种载流子的第二电流栅电极移动到电荷捕获层中，直到第二电流的值至少为第一电流值的一半。

8. 发明申请

US20090097317A1 Integrated Circuit Having NAND Memory Cell Strings 有权
标题翻译：具有NAND存储器单元串的集成电路
公开(公告)号：US20090097317A1
公开(公告)日：2009-04-16
申请号：US11872655
申请日：2007-10-15
申请人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
发明人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
IPC分类号： G11C16/00 , H01L21/336 , H01L29/788
CPC分类号： G11C16/0483 , G11C16/0475 , H01L27/115 , H01L27/11565 , H01L27/11568
摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.
摘要翻译：本发明的实施例一般涉及用于制造集成电路的集成电路和方法。在本发明的实施例中，提供了具有存储单元的集成电路。存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区旁边的沟槽。

9. 发明申请

US20080237694A1 Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module 审中-公开
标题翻译：集成电路，电池，电池布置，集成电路的制造方法，电池的制造方法，存储器模块
公开(公告)号：US20080237694A1
公开(公告)日：2008-10-02
申请号：US11728960
申请日：2007-03-27
申请人： Michael Specht , Nicolas Nagel , Josef Willer
发明人： Michael Specht , Nicolas Nagel , Josef Willer
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , G11C16/0466 , H01L29/513
摘要： The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.
摘要翻译：本发明涉及集成电路，单元，单元布置，集成电路的制造方法，单元的制造方法以及存储器模块。在本发明的实施例中，提供了具有单元的集成电路，该单元包括低k电介质层，设置在低k电介质层上方的第一高k电介质层，设置在第一高k电介质层和设置在电荷捕获层上方的第二高k电介质层。

10. 发明申请

US20080225587A1 Integrated Circuits, Methods for Manufacturing Integrated Circuits, Integrated Memory Arrays 失效
标题翻译：集成电路，集成电路制造方法，集成存储器阵列
公开(公告)号：US20080225587A1
公开(公告)日：2008-09-18
申请号：US11686211
申请日：2007-03-14
申请人： Nicolas Nagel , Josef Willer
发明人： Nicolas Nagel , Josef Willer
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L21/8221 , H01L27/0688 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578
摘要： The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.
摘要翻译：本发明一般涉及集成电路，集成电路的制造方法以及集成存储器阵列。

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