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1. 发明授权

US07846796B2 Semiconductor devices including buried bit lines 有权
标题翻译：半导体器件包括埋地位线
公开(公告)号：US07846796B2
公开(公告)日：2010-12-07
申请号：US12791692
申请日：2010-06-01
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L21/336 , H01L21/425 , H01L21/44
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other
摘要翻译：半导体器件包括半导体衬底上的多个沟道结构。具有相对侧壁的位线槽限定在多个通道结构中的相邻侧壁之间。多个位线形成在对置的相对的侧壁的相应的一个上，多个位线彼此电隔离

2. 发明授权

US07749840B2 Methods of forming a semiconductor device including buried bit line 有权
标题翻译：形成包括掩埋位线的半导体器件的方法
公开(公告)号：US07749840B2
公开(公告)日：2010-07-06
申请号：US11757906
申请日：2007-06-04
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L21/336 , H01L21/425 , H01L21/44
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.
摘要翻译：形成掩埋布线的方法包括去除半导体衬底以在半导体衬底中形成凹槽。使用无电沉积技术在凹槽的内壁上形成金属层。对具有金属层的基板进行硅化处理，从而在槽的内壁上形成金属硅化物层。

3. 发明申请

US20070295995A1 METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING BURIED BIT LINES 有权
标题翻译：形成包含BINIIT位线的半导体器件的方法
公开(公告)号：US20070295995A1
公开(公告)日：2007-12-27
申请号：US11757906
申请日：2007-06-04
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L27/10 , H01L21/44
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.
摘要翻译：形成掩埋布线的方法包括去除半导体衬底以在半导体衬底中形成凹槽。使用无电沉积技术在凹槽的内壁上形成金属层。对具有金属层的基板进行硅化处理，从而在槽的内壁上形成金属硅化物层。

4. 发明申请

US20100237423A1 SEMICONDUCTOR DEVICES INCLUDING BURIED BIT LINES 有权
标题翻译：半导体器件，包括BINIIT位线
公开(公告)号：US20100237423A1
公开(公告)日：2010-09-23
申请号：US12791692
申请日：2010-06-01
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L27/088
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other
摘要翻译：半导体器件包括半导体衬底上的多个沟道结构。具有相对侧壁的位线槽限定在多个通道结构中的相邻侧壁之间。多个位线形成在对置的相对的侧壁的相应的一个上，多个位线彼此电隔离

5. 发明申请

US20080020567A1 Method of Manufacturing a Semiconductor Device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080020567A1
公开(公告)日：2008-01-24
申请号：US11777536
申请日：2007-07-13
申请人： Eun-Ji Jung , Jong-Ho Yun , Dae-Yong Kim , Hyun-Su Kim , Byung-Hee Kim , Eun-Ok Lee
发明人： Eun-Ji Jung , Jong-Ho Yun , Dae-Yong Kim , Hyun-Su Kim , Byung-Hee Kim , Eun-Ok Lee
IPC分类号： H01L21/441
CPC分类号： H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： Provided are methods of manufacturing a semiconductor device. Some embodiments of such methods may include forming a preliminary gate pattern on a substrate. The preliminary gate pattern may include silicon. Methods may include forming an insulation layer pattern on the substrate after forming the preliminary gate pattern. The insulation layer pattern exposes an upper face of the preliminary gate pattern. Methods may include forming a metal layer on the upper face of the preliminary gate pattern via an electroless plating process. Methods may include forming a gate pattern including a metal silicide from a reaction between the preliminary gate pattern and the metal layer by performing a heat treatment process.
摘要翻译：提供制造半导体器件的方法。这种方法的一些实施例可以包括在衬底上形成初步栅极图案。初步栅极图案可以包括硅。方法可以包括在形成初步栅极图案之后在衬底上形成绝缘层图案。绝缘层图案露出初步栅极图案的上表面。方法可以包括通过化学镀处理在预选择栅极图案的上表面上形成金属层。方法可以包括通过进行热处理工艺从预选栅极图案和金属层之间的反应形成包括金属硅化物的栅极图案。

6. 发明申请

US20070281424A1 SEMICONDUCTOR DEVICE AND METHOD OF ITS FORMATION 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20070281424A1
公开(公告)日：2007-12-06
申请号：US11750699
申请日：2007-05-18
申请人： Hyun-Su Kim , Dae-Yong Kim , Eun-Ji Jung , Eun-Ok Lee , Byung-Hee Kim , Jong-Ho Yun
发明人： Hyun-Su Kim , Dae-Yong Kim , Eun-Ji Jung , Eun-Ok Lee , Byung-Hee Kim , Jong-Ho Yun
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/517 , H01L29/6653 , H01L29/6659
摘要： In an embodiment a first silicon pattern and a second silicon pattern are formed on a substrate. The second silicon pattern has a lower top surface than the first silicon pattern. A first spacer covering a sidewall of the first silicon pattern is formed and a second spacer covering a sidewall of the second silicon pattern is formed. A silicide process is performed to silicidize the first silicon pattern and the second silicon pattern. Work functions of the first and second silicon patterns can be controlled and optimized by controlling the composition of the first and second silicon patterns.
摘要翻译：在一个实施例中，在衬底上形成第一硅图案和第二硅图案。第二硅图案具有比第一硅图案更低的顶表面。形成覆盖第一硅图案的侧壁的第一间隔物，并且形成覆盖第二硅图案的侧壁的第二间隔物。执行硅化处理以硅化第一硅图案和第二硅图案。可以通过控制第一和第二硅图案的组成来控制和优化第一和第二硅图案的功能。

7. 发明申请

US20080211038A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080211038A1
公开(公告)日：2008-09-04
申请号：US11965420
申请日：2007-12-27
申请人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
发明人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成初步栅极图案。初步栅极图案包括栅极氧化物图案，导电图案和牺牲绝缘图案。该方法还包括在初步栅极图案的相对侧壁上形成间隔物，形成层间电介质图案以暴露牺牲绝缘图案，去除牺牲绝缘图案以形成露出导电图案的开口，将导电图案转变为金属硅化物并且沿着开口的内部轮廓形成金属阻挡图案和金属导电图案以填充包括金属阻挡图案的开口。金属硅化物层和金属导电图案构成栅电极。

8. 发明授权

US07638433B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07638433B2
公开(公告)日：2009-12-29
申请号：US11965420
申请日：2007-12-27
申请人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
发明人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
IPC分类号： H01L21/302 , H01L21/461 , H01L29/40
CPC分类号： H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成初步栅极图案。初步栅极图案包括栅极氧化物图案，导电图案和牺牲绝缘图案。该方法还包括在初步栅极图案的相对侧壁上形成间隔物，形成层间电介质图案以暴露牺牲绝缘图案，去除牺牲绝缘图案以形成露出导电图案的开口，将导电图案转变为金属硅化物并且沿着开口的内部轮廓形成金属阻挡图案和金属导电图案以填充包括金属阻挡图案的开口。金属硅化物层和金属导电图案构成栅电极。

9. 发明申请

US20090233439A1 Method of forming an ohmic layer and method of forming a metal wiring of a semiconductor device using the same 审中-公开
标题翻译：形成欧姆层的方法和使用该欧姆层的半导体器件的金属布线的形成方法
公开(公告)号：US20090233439A1
公开(公告)日：2009-09-17
申请号：US12382008
申请日：2009-03-05
申请人： Myung-Beom Park , Ki-Hag Lee , Hyun-Su Kim , Eun-Ok Lee , Kyoo-Chul Cho , Jung-Sik Choi , Byung-Hee Kim , Dae-Yong Kim
发明人： Myung-Beom Park , Ki-Hag Lee , Hyun-Su Kim , Eun-Ok Lee , Kyoo-Chul Cho , Jung-Sik Choi , Byung-Hee Kim , Dae-Yong Kim
IPC分类号： H01L21/768
CPC分类号： H01L21/28556 , C23C16/18 , H01L21/28562 , H01L21/76843
摘要： A metal organic precursor represented by a formula of R1-CpML is provided onto a substrate having a conductive pattern including silicon. Here, R1 is an alkyl group substituent of Cp, R1 including methyl, ethyl, propyl, pentamethyl, pentaethyl, diethyl, dimethyl or dipropyl, Cp is cyclopentadienyl, M includes nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt) zirconium (Zr) or ruthenium (Ru), and L is at least one ligand, the at least one ligand including a carbonyl. A deposition process is performed using the metal organic precursor to form a preliminary metal silicide layer and a metal layer on the substrate. The preliminary metal silicidation layer is formed on the conductive pattern. The preliminary metal silicide layer is transformed into a metal silicide layer.
摘要翻译：将由式R1-CpML表示的金属有机前体提供到具有包括硅的导电图案的基板上。这里，R1是Cp的烷基取代基，R1包括甲基，乙基，丙基，五甲基，五乙基，二乙基，二甲基或二丙基，Cp是环戊二烯基，M包括镍（Ni），钴（Co），钛（Ti）铂（Pt）锆（Zr）或钌（Ru），L是至少一种配体，所述至少一种配体包括羰基。使用金属有机前体进行沉积工艺，以在衬底上形成初步金属硅化物层和金属层。在导电图案上形成预备金属硅化层。将初级金属硅化物层转变成金属硅化物层。

10. 发明申请

US20110092060A1 METHODS OF FORMING WIRING STRUCTURES 有权
标题翻译：形成接线结构的方法
公开(公告)号：US20110092060A1
公开(公告)日：2011-04-21
申请号：US12836081
申请日：2010-07-14
申请人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
发明人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L29/66621 , H01L21/76831 , H01L21/76885 , H01L21/76889 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L29/4236 , H01L29/665 , H01L29/78
摘要： A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.
摘要翻译：一种半导体存储器布线方法，包括：接收具有单元阵列区域和外围电路区域的基板; 在衬底上沉积第一绝缘层; 在所述电池阵列区域中形成第一接触插塞，所述第一接触插塞具有延伸穿过所述第一绝缘层的第一导电材料; 在形成第一接触插塞的基本上同时形成第一细长导线，所述第一细长导线具有直接覆盖并与第一接触插塞一体化的第一导电材料; 在形成第一接触插塞的基本上相同的时间在外围电路区域中形成第二接触插塞，第二接触插塞具有延伸穿过第一绝缘层的第一导电材料; 并且在与形成所述第二接触插塞的基本同时形成第二细长导电线，所述第二细长导电线具有直接覆盖并与所述第二接触插塞一体化的所述第一导电材料。

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