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1. 发明申请

US20090265154A1 SIMULATION OF DIGITAL CIRCUITS 失效
标题翻译：数字电路仿真
公开(公告)号：US20090265154A1
公开(公告)日：2009-10-22
申请号：US12103770
申请日：2008-04-16
申请人： John Joseph Bergkvist, JR. , Serafino Bueti , Francis A. Kampf , Douglas Thomas Massey
发明人： John Joseph Bergkvist, JR. , Serafino Bueti , Francis A. Kampf , Douglas Thomas Massey
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.
摘要翻译：一种模拟电路的方法。该方法包括响应于在第一时间点的第一模式改变触发事件和响应于在第一时间点之后的第二时间点的第一数据传输触发事件，生成至少第一随机值的随机值和第二随机值。响应于产生的随机值是第一随机值，将电路的输入的第一输入值分配给电路的输出。响应于产生的随机值是第二随机值，维持电路的输出的输出值。响应于在第二时间点之后的第三时间点的第二数据传输触发事件，将电路的输入的第二输入值分配给电路的输出。

2. 发明授权

US08234104B2 Simulation of digital circuits 失效
标题翻译：数字电路仿真
公开(公告)号：US08234104B2
公开(公告)日：2012-07-31
申请号：US12103770
申请日：2008-04-16
申请人： John Joseph Bergkvist, Jr. , Serafino Bueti , Francis A. Kampf , Douglas Thomas Massey
发明人： John Joseph Bergkvist, Jr. , Serafino Bueti , Francis A. Kampf , Douglas Thomas Massey
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.
摘要翻译：一种模拟电路的方法。该方法包括响应于在第一时间点的第一模式改变触发事件和响应于在第一时间点之后的第二时间点的第一数据传输触发事件，生成至少第一随机值的随机值和第二随机值。响应于产生的随机值是第一随机值，将电路的输入的第一输入值分配给电路的输出。响应于产生的随机值是第二随机值，维持电路的输出的输出值。响应于在第二时间点之后的第三时间点的第二数据传输触发事件，电路的输入的第二输入值被分配给电路的输出。

3. 发明授权

US08347019B2 Structure for hardware assisted bus state transition circuit using content addressable memories 失效
标题翻译：使用内容可寻址存储器的硬件辅助总线状态转换电路的结构
公开(公告)号：US08347019B2
公开(公告)日：2013-01-01
申请号：US12122321
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4059
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

4. 发明申请

US20090094566A1 DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM 审中-公开
标题翻译：芯片识别系统设计结构
公开(公告)号：US20090094566A1
公开(公告)日：2009-04-09
申请号：US12105883
申请日：2008-04-18
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06K19/067
摘要： Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了用于片上识别电路的设计结构。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

5. 发明申请

US20090091351A1 CHIP IDENTIFICATION SYSTEM AND METHOD 有权
标题翻译：芯片识别系统和方法
公开(公告)号：US20090091351A1
公开(公告)日：2009-04-09
申请号：US11869179
申请日：2007-10-09
申请人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： H03K19/00 , H01L23/544
CPC分类号： H01L23/544 , H01L23/5286 , H01L2223/5444 , H01L2924/0002 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了片上识别电路的实施例。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

6. 发明授权

US07511548B2 Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees 失效
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法
公开(公告)号：US07511548B2
公开(公告)日：2009-03-31
申请号：US11610963
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F17/5045 , G06F2217/62
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了一种用于提供平衡负载的时钟分配网络，结构和方法。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

7. 发明申请

US20080282015A1 DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT USING CONTENT ADDRESSABLE MEMORIES 失效
标题翻译：硬件辅助总线转换电路使用内部可寻址存储器的设计结构
公开(公告)号：US20080282015A1
公开(公告)日：2008-11-13
申请号：US12122321
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F13/40
CPC分类号： G06F13/4059
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

8. 发明申请

US20080229266A1 Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构
公开(公告)号：US20080229266A1
公开(公告)日：2008-09-18
申请号：US12129773
申请日：2008-05-30
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

9. 发明申请

US20080143416A1 Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法
公开(公告)号：US20080143416A1
公开(公告)日：2008-06-19
申请号：US11610848
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F1/04 , G06F1/10
CPC分类号： G06F1/10
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了一种用于提供平衡负载的时钟分配网络，结构和方法。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

10. 发明申请

US20070245290A1 METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-QUALIFIED EXPOSURE MASKS FOR SELECTED BLOCKS OF CIRCUITRY 失效
标题翻译：使用预先制作的集成电路的方法和用于选择的电路块的预先准许的接触掩模
公开(公告)号：US20070245290A1
公开(公告)日：2007-10-18
申请号：US11279666
申请日：2006-04-13
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/84
摘要： Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.
摘要翻译：公开了一种制造方法的实施例，其建立用于图案化满足已确定的性能和时序要求的不同电路块的预制和预先限定的掩模库。该方法的实施例使用多个掩模的步进曝光，包括从该库选择的至少一个掩模，以将芯片设计图案化到硅晶片上，其中芯片设计由两个或更多个互连的电路块组成。因此，对于给定的集成电路设计，可以从库中选择预制/预先限定的掩模，以对设计的一个，一些或所有电路块进行图案化。可选地，附加掩模可以被特别地制造并且被限定以在设计中对其他电路块（例如，应用专用逻辑）进行图案化。以这种方式图案化的电路块可通过通用或定制界面电连接，以完成芯片设计。

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