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1. 发明申请

US20130315022A1 MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE 有权
标题翻译：具有全球和本地信号缓存的多银行随机存取存储器结构，用于改进性能
公开(公告)号：US20130315022A1
公开(公告)日：2013-11-28
申请号：US13479448
申请日：2012-05-24
申请人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
发明人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译：公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲并且因此是真实的信号。在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。

2. 发明授权

US06348827B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06348827B1
公开(公告)日：2002-02-19
申请号：US09501216
申请日：2000-02-10
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： H03H1126
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源FET的开关器件接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

3. 发明授权

US08902679B2 Memory array with on and off-state wordline voltages having different temperature coefficients 有权
标题翻译：具有不同温度系数的开状态和截止状态字线电压的存储器阵列
公开(公告)号：US08902679B2
公开(公告)日：2014-12-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
IPC分类号： G11C5/14 , G11C8/08 , H02J1/10
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译：公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。还公开了一种操作存储器阵列结构的方法。

4. 发明授权

US08649239B2 Multi-bank random access memory structure with global and local signal buffering for improved performance 有权
标题翻译：具有全局和本地信号缓冲的多存储体随机存取存储器结构，以提高性能
公开(公告)号：US08649239B2
公开(公告)日：2014-02-11
申请号：US13479448
申请日：2012-05-24
申请人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
发明人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译：公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲并且因此是真实的信号。在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。

5. 发明申请

US20140003164A1 MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERENT TEMPERATURE COEFFICIENTS 有权
标题翻译：具有开启和关闭状态的存储器阵列具有不同温度系数的字线电压
公开(公告)号：US20140003164A1
公开(公告)日：2014-01-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
IPC分类号： G11C5/14 , H02J1/10 , G11C8/08
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译：公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。还公开了一种操作存储器阵列结构的方法。

6. 发明授权

US06400202B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06400202B1
公开(公告)日：2002-06-04
申请号：US09988846
申请日：2001-11-19
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： G06F104
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源PET的开关装置接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

7. 发明授权

US08724365B2 Programmable semiconductor device 有权
标题翻译：可编程半导体器件
公开(公告)号：US08724365B2
公开(公告)日：2014-05-13
申请号：US13427162
申请日：2012-03-22
申请人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
发明人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译：可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

8. 发明授权

US08027207B2 Leakage compensated reference voltage generation system 有权
标题翻译：泄漏补偿参考电压发生系统
公开(公告)号：US08027207B2
公开(公告)日：2011-09-27
申请号：US12639454
申请日：2009-12-16
申请人： John A. Fifield , Harold Pilo
发明人： John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C17/16 , G11C5/147 , G11C7/062 , G11C7/12 , G11C17/18 , G11C29/02 , G11C29/021 , G11C29/028
摘要： An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.
摘要翻译：电熔丝感测电路采用单端感测方案，其中参考电压被补偿以进行泄漏。参考电压发生器包括与所选位线上拉电阻相似的上拉电阻。由于通过选择位线上拉电阻来调整感测跳变点，一对上拉电阻和下拉电阻一起调节，以调整参考电压发生器的阻抗。包括比特单元的并联连接的泄漏路径模拟结构被添加到参考电压发生器。泄漏路径模拟结构模仿电子熔丝阵列中的位线上的位单元。位线上的漏电流将位线电压抵消一定的误差电压。在存在泄漏的情况下，参考电压也被误差电压的一部分偏移以平衡'1'和'0'余量水平的偏移。

9. 发明授权

US07917806B2 System and method for indicating status of an on-chip power supply system 有权
标题翻译：用于指示片上电源系统状态的系统和方法
公开(公告)号：US07917806B2
公开(公告)日：2011-03-29
申请号：US11958680
申请日：2007-12-18
申请人： Darren L. Anand , John A. Fifield , Kevin W. Gorman
发明人： Darren L. Anand , John A. Fifield , Kevin W. Gorman
IPC分类号： G06F11/00
CPC分类号： G01R19/16552 , G11C11/401 , G11C29/02 , G11C29/021 , G11C29/44 , G11C2029/0401 , G11C2029/4402
摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.
摘要翻译：多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。接收数字符合性信号，每个合规信号与多个片上电源之一相关联。每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。输出电源状态信号。如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。

10. 发明授权

US07687883B2 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US07687883B2
公开(公告)日：2010-03-30
申请号：US11627723
申请日：2007-01-26
申请人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
发明人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

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