专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07202164B2 Method of forming ultra thin silicon oxynitride for gate dielectric applications 有权
标题翻译：形成用于栅极电介质应用的超薄氮氧化硅的方法
公开(公告)号：US07202164B2
公开(公告)日：2007-04-10
申请号：US10992894
申请日：2004-11-19
申请人： Jinping Liu , Hwa Weng Koh , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jinping Liu , Hwa Weng Koh , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/0214 , H01L21/02238 , H01L21/02332 , H01L21/265 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.
摘要翻译：公开了一种形成栅介质层的方法。该方法包括以下步骤。提供了具有硅区域的衬底，所述硅区域包含要在其上设置栅极电介质的表面。在表面上形成氧化物。在氧化物层上形成硅层。进行氮化处理。可以进行可选的高温退火步骤。

2. 发明授权

US07338886B2 Implantation-less approach to fabricating strained semiconductor on isolation wafers 有权
标题翻译：无离子方法在隔离晶圆上制造应变半导体
公开(公告)号：US07338886B2
公开(公告)日：2008-03-04
申请号：US11107712
申请日：2005-04-15
申请人： Jinping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jinping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02395 , H01L21/02447 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/76262 , H01L29/78 , Y10S438/933
摘要： A method of fabricating a semiconductor substrate includes forming a buffer layer on the substrate. A Ge containing layer, such as a SiGe is formed over the buffer layer. The buffer layer includes defects at the interface of the substrate and buffer layer. The substrate is oxidized to transform the buffer layer to a buried oxide layer.
摘要翻译：制造半导体衬底的方法包括在衬底上形成缓冲层。在缓冲层之上形成Ge含Ge层，例如SiGe。缓冲层包括在衬底和缓冲层的界面处的缺陷。将衬底氧化以将缓冲层转变成掩埋氧化物层。

3. 发明授权

US07166522B2 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US07166522B2
公开(公告)日：2007-01-23
申请号：US10865433
申请日：2004-06-10
申请人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054
摘要： A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent, overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses. In situ growth of an overlying silicon-germanium layer featuring uniform or non-graded germanium content, results in a relaxed silicon-germanium layer with a minimum of dislocations propagating from the underlying graded silicon-germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

4. 发明授权

US07202140B1 Method to fabricate Ge and Si devices together for performance enhancement 有权
标题翻译：将Ge和Si器件制造在一起以提高性能的方法
公开(公告)号：US07202140B1
公开(公告)日：2007-04-10
申请号：US11297540
申请日：2005-12-07
申请人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
发明人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/30
CPC分类号： H01L27/0688 , H01L21/76256 , H01L21/8221 , H01L21/823807 , H01L2924/00011 , H01L2224/80001
摘要： A method for forming a semiconductor structure having devices formed on both sides. A first substrate and a second substrate are provided. The first substrate is preferably comprised of Ge. The second substrate is preferably comprised of silicon. We form a first dielectric layer over the first substrate. We form a first insulating layer over the second substrate. We bond the first dielectric layer and the first dielectric layer to form a first structure. The first structure comprised of the first substrate, an insulation layer (combined first dielectric and first insulating layers) and the second substrate. We reduce the thickness of the first substrate. We form via plugs through the first substrate and the insulation layer and at least partially through the second substrate. We form first active devices on the surface of the first substrate. We form a first capping layer over the first active devices and the first substrate. We reduce the thickness of the second substrate to expose the via plugs. We form second active devices on the second substrate.
摘要翻译：一种用于形成具有形成在两侧的器件的半导体结构的方法。提供第一基板和第二基板。第一衬底优选由Ge组成。第二衬底优选由硅组成。我们在第一衬底上形成第一电介质层。我们在第二衬底上形成第一绝缘层。我们键合第一介电层和第一介电层以形成第一结构。第一结构包括第一基底，绝缘层（组合的第一介电层和第一绝缘层）和第二基底。我们减少第一个基板的厚度。我们通过插塞穿过第一基底和绝缘层形成，并且至少部分地穿过第二基底。我们在第一衬底的表面上形成第一有源器件。我们在第一有源器件和第一衬底上形成第一覆盖层。我们减小第二基板的厚度以露出通孔塞。我们在第二个基板上形成第二个有源器件。

5. 发明授权

US06995078B2 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US06995078B2
公开(公告)日：2006-02-07
申请号：US10763305
申请日：2004-01-23
申请人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses. In situ growth of an overlying silicon—germanium layer featuring uniform or non—graded germanium content, results in a relaxed silicon—germanium layer with a minimum of dislocations propagating from the underlying graded silicon—germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

6. 发明授权

US07326609B2 Semiconductor device and fabrication method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07326609B2
公开(公告)日：2008-02-05
申请号：US10908328
申请日：2005-05-06
申请人： Purakh Raj Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
发明人： Purakh Raj Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823857 , H01L27/11 , H01L29/66545 , H01L29/7833
摘要： A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.
摘要翻译：用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。牺牲第一栅极形成在第一区域中。源极/漏极形成在第一区域中。第二区域栅极电介质形成在第二区域中。第二区域栅极形成在第二区域栅极电介质上。在第二区域中形成第二区域源极/漏极。在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。牺牲的第一个门被暴露。通过去除牺牲第一栅极形成栅极空间。在栅极空间中形成第一区域栅极电介质。第一区栅极形成在第一区栅极电介质上。牺牲层被去除。

7. 发明授权

US07256112B2 Laser activation of implanted contact plug for memory bitline fabrication 有权
标题翻译：用于存储器位线制造的植入接触插塞的激光激活
公开(公告)号：US07256112B2
公开(公告)日：2007-08-14
申请号：US11039429
申请日：2005-01-20
申请人： Yung Fu Chong , Dong Kyun Sohn , Liang Choo Hsia
发明人： Yung Fu Chong , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/42
CPC分类号： H01L27/105 , H01L21/28512 , H01L21/76897 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/7833
摘要： An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening. We perform a bitline contact plug implant to from a doped contact region under the opening. We activate the doped contact region to form an activated doped contact region using a laser irradiation process. The laser irradiation process improves the electrical activation of the doped contact region without interfering with the silicide and S/D regions of the logic devices.
摘要翻译：使用激光照射激活过程形成用于存储器件的位线接触区域和位线接触插塞的示例性方法。示例实施例包括：提供具有逻辑区域和SONOS存储器区域的衬底。在存储区域中形成存储器晶体管，该存储晶体管由存储栅极电介质，存储栅极电极，存储器LDD区域，存储器栅电极的侧壁上的存储器间隔构成。然后，我们执行“存储单元源线”注入，以在与存储器栅电极相邻的存储器区域中形成存储器源极线。我们在存储器栅电极和存储器源极线上形成硅化物。我们在衬底表面上形成一个ILD电介质层。我们在存储器区域中的存储器漏极上的ILD电介质层中形成接触开口。我们蚀刻在与存储栅电极相邻的漏极区中的衬底中的开口。开口第一次暴露存储单元并暴露开口侧壁上的存储器漏极。我们从开口下方的掺杂接触区域执行位线接触插入注入。我们激活掺杂接触区域，以使用激光照射工艺形成激活的掺杂接触区域。激光照射过程改善了掺杂接触区域的电激活，而不会干扰逻辑器件的硅化物和S / D区域。

8. 发明授权

US07645687B2 Method to fabricate variable work function gates for FUSI devices 有权
标题翻译：为FUSI设备制造可变功能门的方法
公开(公告)号：US07645687B2
公开(公告)日：2010-01-12
申请号：US11039428
申请日：2005-01-20
申请人： Yung Fu Chong , Dong Kyun Sohn , Chew-Hue Ang , Purakh Raj Vermo , Liang Choo Hsia
发明人： Yung Fu Chong , Dong Kyun Sohn , Chew-Hue Ang , Purakh Raj Vermo , Liang Choo Hsia
IPC分类号： H01L21/322
CPC分类号： H01L21/823814 , H01L21/823835 , H01L21/823842
摘要： An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface. We anneal said metal layer to form fully silicided NMOS gate and fully silicided PMOS gate.
摘要翻译：描述了在FUSI设备中制造可变功函数门的实施例。该实施例使用功函数掺杂注入来掺杂多晶硅以实现所需的功函数。选择性外延生长（SEG）用于在源极/漏极区域上形成硅。掺杂的多晶硅栅极被完全硅化以形成具有所需功函数的完全硅化栅极。我们提供具有NMOS区和PMOS区的衬底。我们在所述衬底上形成栅极介电层和栅极层。我们进行（栅极Vt）栅极层注入工艺，将诸如P +，As +，B +，BF 2 +，N +，Sb +，In +，C +，Si +，Ge +或Ar +的杂质注入到NMOS栅极区域中的栅极层栅极中，门区域。我们在所述栅极层上形成覆盖层。我们对所述盖层，所述栅极层和所述栅极电介质层进行图案化以形成NMOS栅极和PMOS栅极。形成间隔物并形成S / D区域。在所述衬底表面上沉积金属。我们退火所述金属层以形成完全硅化的NMOS栅极和完全硅化的PMOS栅极。

9. 发明授权

US07479425B2 Method for forming high-K charge storage device 有权
标题翻译：用于形成高K电荷存储装置的方法
公开(公告)号：US07479425B2
公开(公告)日：2009-01-20
申请号：US11039430
申请日：2005-01-20
申请人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
发明人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/76
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/792
摘要： Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.
摘要翻译：浮栅非易失性存储器件的制造结构和方法。在第一示例性实施例中，我们形成由较低氧化物隧道层和上部氧化铪隧道层组成的底部隧道层; 电荷存储层，其由氧化钽和顶部阻挡层组成，其优选由下部氧化铪存储层和上部氧化物存储层组成。我们在顶部阻挡层上形成栅电极。我们对这些层进行图案化以形成栅极结构并形成源极/漏极区域以完成存储器件。在第二示例实施例中，我们形成浮栅非易失性存储器件，其包括：基本上由氧化硅组成的底部隧道层; 电荷存储层，由钽氧化物构成; 基本上由氧化硅组成的顶部阻挡层; 和栅电极。实施例还包括退火和氮化步骤。

10. 发明申请

US20080087958A1 SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR 审中-公开
标题翻译：带有DOPED晶体管的半导体器件
公开(公告)号：US20080087958A1
公开(公告)日：2008-04-17
申请号：US11951833
申请日：2007-12-06
申请人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
发明人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
IPC分类号： H01L27/088
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823857 , H01L27/11 , H01L29/66545 , H01L29/7833
摘要： A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.
摘要翻译：半导体器件提供具有第一区域和第二区域的衬底。牺牲第一栅极形成在第一区域中。源极/漏极形成在第一区域中。第二区域栅极电介质形成在第二区域中。第二区域栅极形成在第二区域栅极电介质上。在第二区域中形成第二区域源极/漏极。在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。牺牲的第一个门被暴露。通过去除牺牲第一栅极形成栅极空间。在栅极空间中形成第一区域栅极电介质。第一区栅极形成在第一区栅极电介质上。牺牲层被去除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式