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1. 发明授权

US08995178B1 SRAM with embedded ROM 有权
标题翻译： SRAM带嵌入式ROM
公开(公告)号：US08995178B1
公开(公告)日：2015-03-31
申请号：US14069192
申请日：2013-10-31
申请人： Jianan Yang , Brad J. Garni , Mark W. Jetton
发明人： Jianan Yang , Brad J. Garni , Mark W. Jetton
IPC分类号： G11C11/00 , G11C11/412 , H01L27/11
CPC分类号： G11C11/412 , G11C14/0054 , G11C17/12 , H01L27/1104
摘要： An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.
摘要翻译：集成电路包括第一和第二存储器单元，其包括第一上拉晶体管，每个第一上拉晶体管具有耦合到相应的第一和第二阱偏置电压的主体带。第一和第二上拉晶体管的漏极分别耦合到第一真位线和第一互补位线。第二存储器单元包括分别具有耦合到第二阱偏置电压和第一阱偏置电压的主体带的第一和第二上拉晶体管。第一和第二上拉晶体管的漏极电极分别耦合到第二真位线和第二互补位线。在只读存储器（ROM）模式期间，第一阱偏置电压低于第二阱偏置电压，并且在静态随机存取存储器（SRAM）模式期间，第一阱偏置电压与第二阱偏置电压相同。

2. 发明申请

US20140027810A1 SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUES FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件的单事件闭锁预防技术
公开(公告)号：US20140027810A1
公开(公告)日：2014-01-30
申请号：US13560010
申请日：2012-07-27
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
IPC分类号： H01L27/06 , G06F17/50
CPC分类号： H01L27/06 , H01L27/0921
摘要： A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
摘要翻译：用于在半导体器件中寻址单事件闩锁（SEL）的技术包括在半导体器件的集成电路设计中确定寄生硅控整流器（SCR）的位置。在这种情况下，寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npnBJT。该技术还包括在集成电路设计中在第一电源节点和寄生pnp BJT的发射极之间并入第一晶体管。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。第一晶体管限制了在SEL之后由寄生pnp双极结晶体传导的电流。

3. 发明授权

US09123545B2 Semiconductor device with single-event latch-up prevention circuitry 有权
标题翻译：具有单事件闩锁防止电路的半导体器件
公开(公告)号：US09123545B2
公开(公告)日：2015-09-01
申请号：US14188461
申请日：2014-02-24
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston
IPC分类号： H01L29/66 , H01L27/06 , H01L27/092
CPC分类号： H01L27/06 , H01L27/0921
摘要： A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.
摘要翻译：半导体器件包括寄生硅可控整流器（SCR）和第一晶体管。寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npn BJT。第一晶体管耦合在第一电源节点和寄生pnp BJT的发射极之间。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。在单事件闩锁（SEL）事件之后，第一晶体管限制由寄生pnp BJT传导的电流。

4. 发明授权

US08685800B2 Single event latch-up prevention techniques for a semiconductor device 有权
标题翻译：半导体器件的单事件闭锁预防技术
公开(公告)号：US08685800B2
公开(公告)日：2014-04-01
申请号：US13560010
申请日：2012-07-27
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
IPC分类号： H01L21/332
CPC分类号： H01L27/06 , H01L27/0921
摘要： A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
摘要翻译：用于在半导体器件中寻址单事件闩锁（SEL）的技术包括在半导体器件的集成电路设计中确定寄生硅控整流器（SCR）的位置。在这种情况下，寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npnBJT。该技术还包括在集成电路设计中在第一电源节点和寄生pnp BJT的发射极之间并入第一晶体管。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。第一晶体管限制了在SEL之后由寄生pnp双极结晶体传导的电流。

5. 发明授权

US06744663B2 Circuit and method for reading a toggle memory cell 有权
公开(公告)号：US06744663B2
公开(公告)日：2004-06-01
申请号：US10184811
申请日：2002-06-28
申请人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (1300, 1500). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (1300, 1500). The first signal is compared to the second signal to determine the state of the MRAM cell.

6. 发明授权

US06693824B2 Circuit and method of writing a toggle memory 失效
标题翻译：写入切换存储器的电路和方法
公开(公告)号：US06693824B2
公开(公告)日：2004-02-17
申请号：US10186141
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.
摘要翻译：磁阻随机存取存储器以触发方式操作，使得其写入时其逻辑状态从其当前状态翻转到备用状态。这提供了更一致和可靠的编程，因为在切换操作期间的磁过渡能量状态是稳定的。然而，在写入情况下，这意味着在单元被翻转之前，单元格的状态必须被读取并与单元格的期望状态进行比较。如果单元已经处于所需的逻辑状态，则不应写入。写入前的读取时间损失通过在读取时开始写入处理而减少，然后在单元格已经处于所需状态时中止写入步骤。写入实际上可以在单元格上开始并被中止，而不会不利地影响单元的状态。

7. 发明授权

US07292484B1 Sense amplifier with multiple bits sharing a common reference 有权
标题翻译：具有多个位的感应放大器共享一个共同的参考
公开(公告)号：US07292484B1
公开(公告)日：2007-11-06
申请号：US11422774
申请日：2006-06-07
申请人： Thomas W. Andre , Brad J. Garni , Joseph J. Nahas
发明人： Thomas W. Andre , Brad J. Garni , Joseph J. Nahas
IPC分类号： G11C5/14 , G11C7/10 , G11C7/06 , G11C7/02
CPC分类号： G11C7/02 , G11C7/062 , G11C11/1673
摘要： A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.
摘要翻译：存储器电路包括读出放大器，其中单个参考信号与来自两个存储器单元的两个数据信号进行比较。参考信号是以相反逻辑状态的存储单元的组合产生的。数据信号电容与参考信号电容匹配。通过降低但匹配的电容，可以实现高速度和高灵敏度。

8. 发明授权

US06711068B2 Balanced load memory and method of operation 有权
标题翻译：平衡负载记忆和操作方法
公开(公告)号：US06711068B2
公开(公告)日：2004-03-23
申请号：US10184720
申请日：2002-06-28
申请人： Chitra K. Subramanian , Brad J. Garni , Joseph J. Nahas , Halbert S. Lin , Thomas W. Andre
发明人： Chitra K. Subramanian , Brad J. Garni , Joseph J. Nahas , Halbert S. Lin , Thomas W. Andre
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/062 , G11C7/067 , G11C7/14 , G11C2207/005 , G11C2207/063
摘要： A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.
摘要翻译：存储器提供了一种感测方案，其保持数据到感测放大器的路由与参考或参考到读出放大器的路由之间的阻抗平衡。存储器的每个子阵列具有将数据耦合到也与子阵列相邻的数据线的相邻列解码器，并且可以被认为是列解码器的一部分。所选子阵列的数据通过其相邻数据线路由到读出放大器。作为所选子阵列的一部分的参考被耦合到未选择的子阵列的数据线。因此，在MRAM型存储器的情况下，参考优选地紧邻所选数据的位置，穿过相对于由数据采取的路由阻抗平衡的读出放大器的路线。

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