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1. 发明授权

US08872269B2 Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits 有权
标题翻译：天线电池设计，以防止半导体集成电路中的等离子体感应栅介质损坏
公开(公告)号：US08872269B2
公开(公告)日：2014-10-28
申请号：US13316807
申请日：2011-12-12
申请人： Jen-Hang Yang , Chun-Fu Chen , Pin-Dai Sue , Hui-Zhong Zhuang
发明人： Jen-Hang Yang , Chun-Fu Chen , Pin-Dai Sue , Hui-Zhong Zhuang
IPC分类号： H01L21/70
CPC分类号： H01L21/28008 , H01L21/283 , H01L21/76895 , H01L23/60 , H01L27/0207 , H01L27/0629 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
摘要翻译：提供了一种用于防止等离子体增强的栅极介质故障的天线单元。天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。多晶硅引线可以是一组并联的嵌套多晶硅引线之一。虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。二极管与形成有半导体衬底的半导体衬底形成。源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。

2. 发明申请

US20130113520A1 METHOD AND APPARATUS FOR IMPROVED MULTIPLEXING USING TRI-STATE INVERTER 有权
标题翻译：使用三态逆变器改进多路复用的方法和装置
公开(公告)号：US20130113520A1
公开(公告)日：2013-05-09
申请号：US13291204
申请日：2011-11-08
申请人： Chun-Fu CHEN , Hui-Zhong Zhuang , Jen-Hang Yang
发明人： Chun-Fu CHEN , Hui-Zhong Zhuang , Jen-Hang Yang
IPC分类号： H03K19/02 , H05K3/30
CPC分类号： H03K19/1737 , H01L27/0207 , Y10T29/4913
摘要： A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.
摘要翻译：复用电路包括分别耦合到第一和第二数据输入节点的第一和第二三态反相器。第一和第二三态反相器分别包括耦合在电源和接地节点之间的第一和第二晶体管堆叠。每个堆叠包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管。第一和第二堆叠分别包括第一和第二虚拟晶体管。

3. 发明授权

US08482314B2 Method and apparatus for improved multiplexing using tri-state inverter 有权
标题翻译：使用三态逆变器改进复用的方法和装置
公开(公告)号：US08482314B2
公开(公告)日：2013-07-09
申请号：US13291204
申请日：2011-11-08
申请人： Chun-Fu Chen , Hui-Zhong Zhuang , Jen-Hang Yang
发明人： Chun-Fu Chen , Hui-Zhong Zhuang , Jen-Hang Yang
IPC分类号： H03K19/00
CPC分类号： H03K19/1737 , H01L27/0207 , Y10T29/4913
摘要： A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.
摘要翻译：复用电路包括分别耦合到第一和第二数据输入节点的第一和第二三态反相器。第一和第二三态反相器分别包括耦合在电源和接地节点之间的第一和第二晶体管堆叠。每个堆叠包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管。第一和第二堆叠分别包括第一和第二虚拟晶体管。

4. 发明申请

US20080122036A1 Reverse-biased PN diode decoupling capacitor 有权
标题翻译：反向偏置PN二极管去耦电容
公开(公告)号：US20080122036A1
公开(公告)日：2008-05-29
申请号：US11502094
申请日：2006-08-10
申请人： Hsien-Te Chen , Jen-Hang Yang , Chun-Hui Tai
发明人： Hsien-Te Chen , Jen-Hang Yang , Chun-Hui Tai
IPC分类号： H01L29/93
CPC分类号： H01L29/8611 , H01L27/0629 , H01L27/0805 , H01L27/0814
摘要： This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.
摘要翻译：本发明公开了一种集成电路中的去耦电容器，其包括多个专用PN二极管，其总结面积大于专用PN二极管旨在保护的功能器件的总有效面积的十分之一，N型耦合到正电源电压（Vdd）的专用PN二极管的区域和耦合到互补的较低电源电压（Vss）的专用PN二极管的P型区域，其中专用PN二极管被反向偏置。

5. 发明授权

US07496862B2 Method for automatically modifying integrated circuit layout 有权
标题翻译：自动修改集成电路布局的方法
公开(公告)号：US07496862B2
公开(公告)日：2009-02-24
申请号：US11512823
申请日：2006-08-29
申请人： Mi-Chang Chang , Su-Ya Lin , Jen-Hang Yang , Li-Chun Tien
发明人： Mi-Chang Chang , Su-Ya Lin , Jen-Hang Yang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/11807
摘要： This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.
摘要翻译：本发明公开了一种用于自动调整一个类型的MOS IC单元的单元布局高度和晶体管宽度的方法，所述方法包括以下步骤：对至少一个这样的单元进行布尔逻辑运算：识别一个或多个MOS晶体管有源区（OD）和在OD层中的一个或多个功率OD，将预定方向上的MOS晶体管OD扩展第一预定量，将预定方向上的功率OD移动第二预定量，将预定的一个或多个MOS晶体管栅极区域扩展方向移动第三预定量，将一个或多个功率OD触点沿预定方向移动大约第二预定量，以及通过电子接触在一个金属层中直接连接到OD层的金属层中拉伸一个或多个金属区域（M1），以预定的方式在预定方向上。

6. 发明申请

US20080059916A1 Method for automatically modifying integrated circuit layout 有权
标题翻译：自动修改集成电路布局的方法
公开(公告)号：US20080059916A1
公开(公告)日：2008-03-06
申请号：US11512823
申请日：2006-08-29
申请人： Mi-Chang Chang , Su-Ya Lin , Jen-Hang Yang , Li-Chun Tien
发明人： Mi-Chang Chang , Su-Ya Lin , Jen-Hang Yang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/11807
摘要： This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.
摘要翻译：本发明公开了一种用于自动调整一个类型的MOS IC单元的单元布局高度和晶体管宽度的方法，所述方法包括以下步骤：对至少一个这样的单元进行布尔逻辑运算：识别一个或多个MOS晶体管有源区（OD）和在OD层中的一个或多个功率OD，将预定方向上的MOS晶体管OD扩展第一预定量，将预定方向上的功率OD移动第二预定量，将预定的一个或多个MOS晶体管栅极区域扩展方向移动第三预定量，将一个或多个功率OD触点沿预定方向移动大约第二预定量，以及通过电子接触在一个金属层中直接连接到OD层的金属层中拉伸一个或多个金属区域（M1），以预定的方式在预定方向上。

7. 发明授权

US08552785B2 Pulse generator 有权
标题翻译：脉冲发生器
公开(公告)号：US08552785B2
公开(公告)日：2013-10-08
申请号：US13292124
申请日：2011-11-09
申请人： Ming-Zhang Kuo , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
发明人： Ming-Zhang Kuo , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
IPC分类号： G06F1/04
CPC分类号： H03K3/033
摘要： A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
摘要翻译：电路包括逻辑门和锁存器。逻辑门被配置为在第一输入处接收时钟信号。锁存器被布置在逻辑门的反馈回路中，并被配置为响应于由逻辑门输出的信号和时钟信号而将反馈信号输出到逻辑门的第二输入端。电路被配置为基于时钟信号的上升沿或下降沿中的一个输出脉冲信号。

8. 发明申请

US20130113537A1 PULSE GENERATOR 有权
标题翻译：脉冲发生器
公开(公告)号：US20130113537A1
公开(公告)日：2013-05-09
申请号：US13292124
申请日：2011-11-09
申请人： Ming-Zhang KUO , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
发明人： Ming-Zhang KUO , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
IPC分类号： H03K3/017 , H03K3/00 , H03H11/26
CPC分类号： H03K3/033
摘要： A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
摘要翻译：电路包括逻辑门和锁存器。逻辑门被配置为在第一输入处接收时钟信号。锁存器被布置在逻辑门的反馈回路中，并被配置为响应于由逻辑门输出的信号和时钟信号而将反馈信号输出到逻辑门的第二输入端。电路被配置为基于时钟信号的上升沿或下降沿中的一个输出脉冲信号。

9. 发明授权

US07550820B2 Reverse-biased PN diode decoupling capacitor 有权
标题翻译：反向偏置PN二极管去耦电容
公开(公告)号：US07550820B2
公开(公告)日：2009-06-23
申请号：US11502094
申请日：2006-08-10
申请人： Hsien-Te Chen , Jen-Hang Yang , Chun-Hui Tai
发明人： Hsien-Te Chen , Jen-Hang Yang , Chun-Hui Tai
IPC分类号： H01L29/93
CPC分类号： H01L29/8611 , H01L27/0629 , H01L27/0805 , H01L27/0814
摘要： This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.
摘要翻译：本发明公开了一种集成电路中的去耦电容器，其包括多个专用PN二极管，其总结面积大于专用PN二极管旨在保护的功能器件的总有效面积的十分之一，N型耦合到正电源电压（Vdd）的专用PN二极管的区域和耦合到互补的较低电源电压（Vss）的专用PN二极管的P型区域，其中专用PN二极管被反向偏置。

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