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    • 6. 发明申请
    • DUTY CYCLE CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
    • 半导体存储器的占空比校正电路
    • US20090302912A1
    • 2009-12-10
    • US12346683
    • 2008-12-30
    • Seong Jun Lee
    • Seong Jun Lee
    • H03K3/017
    • H03K5/1565G11C7/22G11C7/222
    • A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock signal as a correction clock signal, a duty ratio detecting unit configured to count first and second counting signals in response to a duty ratio of the correction clock signal when a pump enable signal is enabled, a pump enable signal generating unit configured to generate the pump enable signal in response to the duty ratio of the correction clock signal, and a reference voltage generating unit configured to generate the first and second reference voltages in response to the first and second counting signals.
    • 半导体存储装置的占空比校正电路包括占空比校正单元,其被配置为根据第一参考电压和第二参考电压的电平来校正时钟信号的占空比,并将时钟信号作为校正时钟输出 信号,占空比检测单元,被配置为当启用泵使能信号时响应于所述校正时钟信号的占空比来对第一和第二计数信号进行计数;泵使能信号生成单元,被配置为响应于 校正时钟信号的占空比,以及被配置为响应于第一和第二计数信号而产生第一和第二参考电压的参考电压产生单元。