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1. 发明授权

US5990910A Method and apparatus for co-processing multi-formatted data 失效
标题翻译：用于协处理多格式数据的方法和装置
公开(公告)号：US5990910A
公开(公告)日：1999-11-23
申请号：US47193
申请日：1998-03-24
申请人： Indra Laksono , Anthony Asaro
发明人： Indra Laksono , Anthony Asaro
IPC分类号： G06F9/30 , G06F9/38 , G06F15/16
CPC分类号： G06F9/30025 , G06F9/3877
摘要： A method and apparatus for co-processing multi-formatted data which begins when a host processor writes data blocks, in a substantially continuous manner, into memory. Each of the data blocks includes a plurality of data elements and each data element has one of a plurality of data formats. As the data block is being stored in memory, a co-processor retrieves selected data elements from the memory. Upon retrieving the selected data elements, the co-processor interprets them to identify the data format. If the data format is consistent with the data format of the co-processor, the co-processor processes the data element without conversion. If, however, the data format of the selected data element is not consistent with the data format of the co-processor, the co-processor converts the format of the selected data element into the format consistent with the co-processor.
摘要翻译：一种用于协处理多格式数据的方法和装置，该方法和装置在主处理器以基本连续的方式将数据块写入存储器时开始。每个数据块包括多个数据元素，并且每个数据元素具有多种数据格式之一。当数据块被存储在存储器中时，协处理器从存储器中检索所选择的数据元素。在检索所选择的数据元素之后，协处理器解释它们以识别数据格式。如果数据格式与协处理器的数据格式一致，则协处理器处理数据元素而不进行转换。然而，如果所选数据元素的数据格式与协处理器的数据格式不一致，则协处理器将所选择的数据元素的格式转换成与协处理器一致的格式。

2. 发明授权

US6124868A Method and apparatus for multiple co-processor utilization of a ring buffer 失效
标题翻译：多个协处理器利用环形缓冲器的方法和装置
公开(公告)号：US6124868A
公开(公告)日：2000-09-26
申请号：US47319
申请日：1998-03-24
申请人： Anthony Asaro , Indra Laksono , James Doyle
发明人： Anthony Asaro , Indra Laksono , James Doyle
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3879
摘要： A method and apparatus for a processing system to utilize a ring buffer includes a host processor, memory, and at least one co-processor. The host processor generates a plurality of data blocks that relates to a particular application (e.g., word processing application, drafting application, presentation application, spreadsheet application, video game application, etc.). The host processor writes data elements of the data blocks into the memory, which is organized in a ring buffer manner. As the host processor enters the data elements into the ring buffer, it updates a head pointer, which indicates the most current address of a data element entered into the ring buffer, in its local cache. The co-processor retrieves the data elements from the ring buffer and performs a co-processor function in support of the particular application. As the co-processor retrieves data elements from the ring buffer, it updates a tail pointer, which indicates the most recently read data element from memory, or executed data element. The co-processor and host processor exchange the updated tail and header pointers as they are updated, such that both the co-processor and host processor have current records of the tail and header pointers.
摘要翻译：用于使用环形缓冲器的处理系统的方法和装置包括主处理器，存储器和至少一个协处理器。主处理器生成与特定应用（例如，文字处理应用，起草应用，呈现应用，电子表格应用，视频游戏应用等）相关的多个数据块。主处理器将数据块的数据元素写入存储器，存储器以环形缓冲器方式组织。当主机处理器将数据元素输入到环形缓冲器中时，它在其本地高速缓存中更新头指针，其指示输入到环形缓冲器中的数据元素的最新地址。协处理器从环形缓冲器中检索数据元素，并执行协处理器功能以支持特定应用。当协处理器从环形缓冲器中检索数据元素时，它更新一个尾部指针，指示最近从存储器读取的数据元素或执行的数据元素。协处理器和主机处理器在更新时交换更新的尾部和标题指针，使得协处理器和主处理器都具有尾部和标题指针的当前记录。

3. 发明授权

US08924617B2 Memory device for providing data in a graphics system and method and apparatus therof 有权
标题翻译：用于在图形系统中提供数据的存储器件以及方法和装置
公开(公告)号：US08924617B2
公开(公告)日：2014-12-30
申请号：US12429833
申请日：2009-04-24
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Anthony Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Anthony Asaro
IPC分类号： G06F13/14 , G09G5/39 , G06T1/60 , G09G5/393
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

4. 发明申请

US20110264934A1 METHOD AND APPARATUS FOR MEMORY POWER MANAGEMENT 有权
标题翻译：用于存储电源管理的方法和装置
公开(公告)号：US20110264934A1
公开(公告)日：2011-10-27
申请号：US12767460
申请日：2010-04-26
申请人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
发明人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
摘要翻译：公开了一种用于电力管理的方法。该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量内存访问请求。如果第一和第二时间量已经过去，则可以断言第一信号。存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

5. 发明申请

US20090077274A1 Multi-Priority Communication in a Differential Serial Communication Link 审中-公开
标题翻译：差分串行通信链路中的多优先通信
公开(公告)号：US20090077274A1
公开(公告)日：2009-03-19
申请号：US11857984
申请日：2007-09-19
申请人： Gordon F. Caruk , Anthony Asaro
发明人： Gordon F. Caruk , Anthony Asaro
IPC分类号： G06F3/00
CPC分类号： G06F13/4278 , Y02D10/14 , Y02D10/151
摘要： A circuit includes a high priority circuit and a non-high priority circuit. The high priority circuit is operative to communicate high priority information to a single path of a differential serial communication link. The non-high priority circuit communicates non-high priority information to the single path. The high priority information is communicated prior to the non-high priority information. In one example, the circuit includes a flow control distributor operatively coupled to the high priority circuit and the non-high priority circuit. The flow control distributor distributes a total number of flow control credits into high priority credits and non-high priority credits. The flow control distributor controls communication of the high priority information based on the high priority credits. The flow control distributor controls communication of the non-high priority information based on the non-high priority credits.
摘要翻译：电路包括高优先级电路和非高优先级电路。高优先级电路用于将高优先级信息传送到差分串行通信链路的单个路径。非高优先级电路将非高优先级信息传送到单路径。在非高优先级信息之前传送高优先级信息。在一个示例中，电路包括可操作地耦合到高优先级电路和非高优先级电路的流量控制分配器。流量控制分配器将总数量的流量控制信用分配到高优先级信用和非高优先级信用。流量控制分配器基于高优先级信用来控制高优先级信息的通信。流量控制分配器基于非高优先级信用来控制非高优先级信息的通信。

6. 发明授权

US09152571B2 All invalidate approach for memory management units 有权
标题翻译：内存管理单元的所有无效方法
公开(公告)号：US09152571B2
公开(公告)日：2015-10-06
申请号：US13563253
申请日：2012-07-31
申请人： Andrew G. Kegel , Mark D. Hummel , Anthony Asaro
发明人： Andrew G. Kegel , Mark D. Hummel , Anthony Asaro
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1081 , G06F2212/683
摘要： An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided.
摘要翻译：提供具有可用于清除高速缓冲存储器的内容的“无效全部”命令的输入/输出存储器管理单元（IOMMU）。缓存存储器可以快速访问以前由进程获取的地址转换数据。典型的高速缓存包括设备表，页表和中断重映射条目。高速缓存存储器数据可能会变得过时或者从安全漏洞或故障设备中泄露出来。在这些情况下，提供了快速清除缓存存储器内容的方法。

7. 发明授权

US08656198B2 Method and apparatus for memory power management 有权
标题翻译：用于存储器电源管理的方法和装置
公开(公告)号：US08656198B2
公开(公告)日：2014-02-18
申请号：US12767460
申请日：2010-04-26
申请人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
发明人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
摘要翻译：公开了一种用于电力管理的方法。该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量内存访问请求。如果第一和第二时间量已经过去，则可以断言第一信号。存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

8. 发明申请

US20130263141A1 Visibility Ordering in a Memory Model for a Unified Computing System 有权
标题翻译：在统一计算系统的内存模型中的可见性排序
公开(公告)号：US20130263141A1
公开(公告)日：2013-10-03
申请号：US13588310
申请日：2012-08-17
申请人： Anthony Asaro , Kevin Normoyle , Mark Hummel
发明人： Anthony Asaro , Kevin Normoyle , Mark Hummel
IPC分类号： G06F9/46
CPC分类号： G06F9/46 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/52
摘要： Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.
摘要翻译：提供了一种允许重新排序配置为允许第一处理器和第二处理器线程访问共享存储器的计算机配置中的操作的可见性顺序的方法。该方法包括以程序顺序接收第一线程中的第一和第二操作，并且基于每个操作的类别允许对共享存储器中的操作的可见性顺序的重新排序。可见性顺序确定共享存储器（第二个线程）中可执行第一和第二操作的存储结果的可见性。

9. 发明授权

US08495300B2 Cache with reload capability after power restoration 有权
标题翻译：电源恢复后具有重新加载功能的缓存
公开(公告)号：US08495300B2
公开(公告)日：2013-07-23
申请号：US12716391
申请日：2010-03-03
申请人： Philip Ng , Jimshed B. Mirza , Anthony Asaro
发明人： Philip Ng , Jimshed B. Mirza , Anthony Asaro
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0868 , G06F2212/1028 , G06F2212/6024 , Y02D10/13
摘要： A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.
摘要翻译：公开了一种用于重新填充缓存的方法和装置。缓存的内容的至少一部分被存储在与高速缓存分开的位置。电源从缓存中删除，并在稍后恢复。在电源恢复到缓存之后，它将重新填充与高速缓存单独存储的高速缓存的内容部分。

10. 发明申请

US20130145055A1 Peripheral Memory Management 审中-公开
标题翻译：外设内存管理
公开(公告)号：US20130145055A1
公开(公告)日：2013-06-06
申请号：US13309753
申请日：2011-12-02
申请人： Andrew Kegel , Mark Hummel , Anthony Asaro , Phillip NG
发明人： Andrew Kegel , Mark Hummel , Anthony Asaro , Phillip NG
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F12/0223 , G06F12/1081 , G06F2213/0058
摘要： The present system enables an input/output (I/O) device to request memory for performing a direct memory access (DMA) of system memory. Further, the system uses an input/output memory management unit (IOMMU) to determine whether or not the system memory is available. The IOMMU notifies an operating system associated with the system memory if the system memory is not available, such that the operating system allocates non-system memory for use by the I/O device to perform the DMA.
摘要翻译：本系统使得输入/输出（I / O）设备能够请求存储器来执行系统存储器的直接存储器访问（DMA）。此外，系统使用输入/输出存储器管理单元（IOMMU）来确定系统存储器是否可用。如果系统内存不可用，IOMMU将通知与系统内存相关联的操作系统，以便操作系统分配非系统内存供I / O设备使用以执行DMA。

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