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1. 发明授权

US09431549B2 Nonvolatile charge trap memory device having a high dielectric constant blocking region 有权
标题翻译：具有高介电常数阻挡区域的非易失性电荷陷阱存储器件
公开(公告)号：US09431549B2
公开(公告)日：2016-08-30
申请号：US13436875
申请日：2012-03-31
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L29/792 , B82Y10/00 , H01L21/28 , H01L29/51 , H01L29/66 , H01L27/115
CPC分类号： H01L29/7923 , B82Y10/00 , H01L21/28282 , H01L27/11578 , H01L29/0676 , H01L29/42392 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66666 , H01L29/66742 , H01L29/66833 , H01L29/78642 , H01L29/78696 , H01L29/792 , H01L29/7926
摘要： An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.
摘要翻译：描述了非易失性电荷陷阱存储器件的实施例。在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。多层阻挡电介质至少包括高K电介质层。

2. 发明授权

US08859374B1 Memory transistor with multiple charge storing layers and a high work function gate electrode 有权
标题翻译：具有多个电荷存储层和高功函数栅电极的存储晶体管
公开(公告)号：US08859374B1
公开(公告)日：2014-10-14
申请号：US13288919
申请日：2011-11-03
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , G11C16/0466 , G11C16/349 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/28035 , H01L21/28282 , H01L27/11573 , H01L29/4234 , H01L29/4916 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.
摘要翻译：提供包括非易失性存储晶体管的半导体器件及其制造方法以改善其性能。在一个实施例中，该方法包括：（i）在其中将形成非易失性存储晶体管的至少第一区域中，在半导体衬底的表面上形成氧化物 - 氧化物 - 氧化物（ONO）电介质叠层， ONO电介质堆叠包括多层电荷存储层; （ii）在要形成金属氧化物半导体（MOS）逻辑晶体管的第二区域中在所述衬底的表面上形成氧化物层; 和（iii）在ONO电介质叠层的表面上形成高功函数栅电极。还公开了其他实施例。

3. 发明授权

US07880219B2 Nonvolatile charge trap memory device having <100> crystal plane channel orientation 有权
标题翻译：具有<100>晶体平面通道取向的非易失性电荷陷阱存储器件
公开(公告)号：US07880219B2
公开(公告)日：2011-02-01
申请号：US11904470
申请日：2007-09-26
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28123 , H01L21/28167 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/045 , H01L29/42324
摘要： A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.
摘要翻译：描述了一种非易失性电荷陷阱存储器件及其形成方法。该器件包括具有<100>晶面取向的沟道长度的沟道区。沟道区域位于一对源极区和漏极区之间，栅极堆叠设置在沟道区的上方。

4. 发明申请

US20080290398A1 Nonvolatile charge trap memory device having <100> crystal plane channel orientation 有权
标题翻译：具有<100>晶体平面通道取向的非易失性电荷陷阱存储器件
公开(公告)号：US20080290398A1
公开(公告)日：2008-11-27
申请号：US11904470
申请日：2007-09-26
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28123 , H01L21/28167 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/045 , H01L29/42324
摘要： A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.
摘要翻译：描述了一种非易失性电荷陷阱存储器件及其形成方法。该器件包括具有<100>晶面取向的通道长度的沟道区域。沟道区域位于一对源极区和漏极区之间，栅极堆叠设置在沟道区的上方。

5. 发明授权

US08633537B2 Memory transistor with multiple charge storing layers and a high work function gate electrode 有权
标题翻译：具有多个电荷存储层和高功函数栅电极的存储晶体管
公开(公告)号：US08633537B2
公开(公告)日：2014-01-21
申请号：US13539466
申请日：2012-07-01
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , B82Y10/00 , G11C16/0466 , H01L21/0214 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L27/11526 , H01L27/11563 , H01L27/11568 , H01L27/11573 , H01L27/11575 , H01L29/0649 , H01L29/0676 , H01L29/42344 , H01L29/4916 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66795 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed.
摘要翻译：提供了包括非易失性存储器的半导体器件及其制造方法以提高其性能。通常，器件包括存储晶体管，其包括电连接形成在衬底中的源极区域和漏极区域的多晶硅沟道区域，设置在沟道区域上方的氧化物氮化物 - 氮化物氧化物（ONNO）堆叠以及高功函数栅电极形成在ONNO堆的表面上。在一个实施方案中，ONNO堆叠包括多层电荷捕获区域，其包括富含氧的第一氮化物层和设置在第一氮化物层上方的无氧的第二氮化物层。还公开了其他实施例。

6. 发明申请

US20130175604A1 NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION 有权
标题翻译：具有高介电常数阻塞区域的非挥发性电荷捕获存储器件
公开(公告)号：US20130175604A1
公开(公告)日：2013-07-11
申请号：US13436875
申请日：2012-03-31
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , B82Y10/00 , H01L21/28282 , H01L27/11578 , H01L29/0676 , H01L29/42392 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66666 , H01L29/66742 , H01L29/66833 , H01L29/78642 , H01L29/78696 , H01L29/792 , H01L29/7926
摘要： An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.
摘要翻译：描述了非易失性电荷陷阱存储器件的实施例。在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。多层阻挡电介质至少包括高K电介质层。

7. 发明授权

US08063434B1 Memory transistor with multiple charge storing layers and a high work function gate electrode 有权
标题翻译：具有多个电荷存储层和高功函数栅电极的存储晶体管
公开(公告)号：US08063434B1
公开(公告)日：2011-11-22
申请号：US12152518
申请日：2008-05-13
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , G11C16/0466 , G11C16/349 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/28035 , H01L21/28282 , H01L27/11573 , H01L29/4234 , H01L29/4916 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： An embodiment of a semiconductor device includes a non-volatile memory transistor including an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate, the ONO dielectric stack comprising a multilayer charge storage layer including a silicon-rich, oxygen-lean top silicon oxynitride layer and a silicon-rich, oxygen-rich bottom silicon oxynitride layer, and a metal oxide semiconductor (MOS) logic transistor including a gate oxide and a high work function gate electrode.
摘要翻译：半导体器件的实施例包括在半导体衬底的表面上包括氧化物 - 氧化物 - 氧化物（ONO）电介质堆叠的非易失性存储晶体管，所述ONO电介质堆叠包括多层电荷存储层，其包含富含硅的氧 - 富硅顶氧氮化硅层和富含硅的富氧底氧氮化硅层，以及包括栅极氧化物和高功函电极电极的金属氧化物半导体（MOS）逻辑晶体管。

8. 发明申请

US20070184597A1 Stress liner for integrated circuits 有权
标题翻译：集成电路应力衬垫
公开(公告)号：US20070184597A1
公开(公告)日：2007-08-09
申请号：US11350160
申请日：2006-02-07
申请人： Igor Polishchuk , Krishnaswamy Ramkumar , Sagy Levy
发明人： Igor Polishchuk , Krishnaswamy Ramkumar , Sagy Levy
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.
摘要翻译：在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

9. 发明授权

US08592891B1 Methods for fabricating semiconductor memory with process induced strain 有权
标题翻译：用工艺诱导应变制造半导体存储器的方法
公开(公告)号：US08592891B1
公开(公告)日：2013-11-26
申请号：US13539463
申请日：2012-07-01
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Byun
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Byun
IPC分类号： H01L29/76
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.
摘要翻译：提供了半导体器件及其制造方法。在一个实施例中，半导体器件包括具有设置在沟道区上方的氧化氮化物 - 氮化物 - 氧化物（ONNO）堆的存储晶体管。 ONNO堆叠包括设置在沟道区上方的隧道介电层，设置在隧道介电层上方的多层电荷捕获区，以及设置在多层电荷俘获区上方的阻挡介质层。多层电荷捕获区域包括基本上无陷阱层，其包含富含氧的氮化物和设置在无阱层之上的陷阱致密层。半导体器件还包括应变诱导结构，其包括设置在ONNO堆叠附近的应变诱导层，以增加多层电荷俘获区域的电荷保留。还公开了其他实施例。

10. 发明授权

US08691648B1 Methods for fabricating semiconductor memory with process induced strain 有权
标题翻译：用工艺诱导应变制造半导体存储器的方法
公开(公告)号：US08691648B1
公开(公告)日：2014-04-08
申请号：US13168711
申请日：2011-06-24
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Soo Byun
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Soo Byun
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/66833 , H01L29/792
摘要： Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.
摘要翻译：提供非易失性半导体存储器及其制造方法以改善其性能。在一个实施例中，该方法包括：（i）在覆盖其中形成的沟道区的衬底的表面上形成用于非易失性存储晶体管的栅极，栅极包括电荷俘获层; 和（ii）在非易失性存储晶体管的栅极上形成应变诱导结构，以增加电荷俘获层的电荷保留。优选地，存储晶体管是包括SONOS栅极堆叠的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）晶体管。更优选地，存储器还包括在衬底上的逻辑晶体管，并且形成应变诱导结构的步骤包括在逻辑晶体管上形成应变诱导结构的步骤。还公开了其他实施例。

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