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1. 发明授权

US08618839B2 Utilizing a sense amplifier to select a suitable circuit 失效
标题翻译：利用读出放大器选择合适的电路
公开(公告)号：US08618839B2
公开(公告)日：2013-12-31
申请号：US13418961
申请日：2012-03-13
申请人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
发明人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
IPC分类号： G01R19/00
CPC分类号： H03F3/45183 , H03F3/45609 , H03F3/68 , H03F2200/408 , H03F2200/78
摘要： Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.
摘要翻译：本发明的实施例提供了一种利用读出放大器来选择合适电路的方法，其中合适的电路产生大于或等于可配置参考电压的电压。放大器增益选择器选择具有输入端，辅助输入，输出，电阻性负载阵列和放大器增益选择器的读出放大器的电压增益。辅助输入用于消除读出放大器的直流（DC）偏移电压。组合逻辑电路将读出放大器的输入端连接到一组电路内的电路的输出端。比较器电路基于读出放大器的输出来确定电路是否产生大于或等于可配置参考电压的电压。

2. 发明申请

US20140035670A1 FET PAIR BASED PHYSICALLY UNCLONABLE FUNCTION (PUF) CIRCUIT WITH A CONSTANT COMMON MODE VOLTAGE 有权
标题翻译：具有恒定通用模式电压的基于FET对的物理不可靠功能（PUF）电路
公开(公告)号：US20140035670A1
公开(公告)日：2014-02-06
申请号：US13566805
申请日：2012-08-03
申请人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
发明人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
IPC分类号： H03F3/45
CPC分类号： G06F7/588 , G09C1/00 , H04L9/0866 , H04L9/3278 , H04L2209/12
摘要： A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.
摘要翻译：公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。电路包括第一n型场效应晶体管（NFET）和第二NFET。电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。电路还包括闭环，其中闭环产生恒定的共模电压。

3. 发明申请

US20130241652A1 UTILIZING A SENSE AMPLIFIER TO SELECT A SUITABLE CIRCUIT 失效
标题翻译：使用感应放大器选择适合的电路
公开(公告)号：US20130241652A1
公开(公告)日：2013-09-19
申请号：US13418961
申请日：2012-03-13
申请人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
发明人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45609 , H03F3/68 , H03F2200/408 , H03F2200/78
摘要： Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.
摘要翻译：本发明的实施例提供了一种利用读出放大器来选择合适电路的方法，其中合适的电路产生大于或等于可配置参考电压的电压。放大器增益选择器选择具有输入端，辅助输入，输出，电阻性负载阵列和放大器增益选择器的读出放大器的电压增益。辅助输入用于消除读出放大器的直流（DC）偏移电压。组合逻辑电路将读出放大器的输入端连接到一组电路内的电路的输出端。比较器电路基于读出放大器的输出来确定电路是否产生大于或等于可配置参考电压的电压。

4. 发明授权

US08941405B2 FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage 有权
标题翻译：基于FET对的物理不可克隆功能（PUF）电路，具有恒定的共模电压
公开(公告)号：US08941405B2
公开(公告)日：2015-01-27
申请号：US13566805
申请日：2012-08-03
申请人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
发明人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
IPC分类号： H03K19/00 , H05K3/00
CPC分类号： G06F7/588 , G09C1/00 , H04L9/0866 , H04L9/3278 , H04L2209/12
摘要： A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.
摘要翻译：公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。电路包括第一n型场效应晶体管（NFET）和第二NFET。电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。电路还包括闭环，其中闭环产生恒定的共模电压。

5. 发明授权

US11942937B2 Pulse-generator-based bias-level sensors for reciprocal quantum logic 有权
公开(公告)号：US11942937B2
公开(公告)日：2024-03-26
申请号：US17736517
申请日：2022-05-04
申请人： Charles Ryan Wallace , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Haitao O. Dai
发明人： Charles Ryan Wallace , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Haitao O. Dai
IPC分类号： H03K19/195 , H03K3/38 , H03K19/17736 , H03K19/20
CPC分类号： H03K19/195 , H03K3/38 , H03K19/1774 , H03K19/17744 , H03K19/20
摘要： Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

6. 发明授权

US11804275B1 Phase-mode bit-addressable sensing register 有权
公开(公告)号：US11804275B1
公开(公告)日：2023-10-31
申请号：US17736564
申请日：2022-05-04
申请人： Alexander Louis Braun , Max E. Nielsen , Daniel George Dosch , Kurt Pleim , Haitao O. Dai , Charles Ryan Wallace
发明人： Alexander Louis Braun , Max E. Nielsen , Daniel George Dosch , Kurt Pleim , Haitao O. Dai , Charles Ryan Wallace
IPC分类号： G11C19/32 , H03L7/081 , H03K3/037 , H03K19/195 , H03L7/08 , H03K3/38
CPC分类号： G11C19/32 , H03K3/037 , H03K3/38 , H03K19/195 , H03L7/0805 , H03L7/0816
摘要： Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

7. 发明授权

US11476842B1 Superconducting current source system 有权
公开(公告)号：US11476842B1
公开(公告)日：2022-10-18
申请号：US17350712
申请日：2021-06-17
申请人： Dipankar Bhattacharya , Donald L. Miller , Haitao O. Dai , Quentin P. Herr
发明人： Dipankar Bhattacharya , Donald L. Miller , Haitao O. Dai , Quentin P. Herr
IPC分类号： H03K3/38 , G06N10/00 , H03K19/195
摘要： One example describes a superconducting current source system comprising a linear flux-shuttle. The linear flux-shuttle includes an input and a plurality of Josephson transmission line (JTL) stages. Each of the JTL stages includes at least one Josephson junction, an output inductor, and a clock input. The linear flux-shuttle can be configured to generate a direct current (DC) output current via the output inductor associated with each of the JTL stages in response to the at least one Josephson junction triggering in a sequence in each of the JTL stages along the linear flux-shuttle in response to receiving an input pulse at the input and in response to a clock signal provided to the clock input in each of the JTL stages.

8. 发明授权

US09876505B1 Superconducting isochronous receiver system 有权
公开(公告)号：US09876505B1
公开(公告)日：2018-01-23
申请号：US15256213
申请日：2016-09-02
申请人： Haitao O. Dai , Quentin P. Herr , Steven B. Shauck , Anna Y. Herr , Randall M. Burnett
发明人： Haitao O. Dai , Quentin P. Herr , Steven B. Shauck , Anna Y. Herr , Randall M. Burnett
IPC分类号： H03K19/195 , G06N99/00 , H04B1/40
CPC分类号： H03K19/195 , G06N99/002 , H03K3/38 , H03K19/1952 , H04B1/40
摘要： An isochronous receiver system is provided and includes a single flux quantum (SFQ) receiver to receive a data signal from a transmission line. The single flux quantum receiver then converts the data signal to an SFQ signal. The system also includes a converter system to convert the SFQ signal to a reciprocal quantum logic (RQL) signal and to phase-align the RQL signal with a sampling phase of an AC clock signal.

9. 发明授权

US12045692B2 Squid stack pulse height bias-level sensor for reciprocal quantum logic 有权
公开(公告)号：US12045692B2
公开(公告)日：2024-07-23
申请号：US17736646
申请日：2022-05-04
申请人： Haitao O. Dai , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Charles Ryan Wallace
发明人： Haitao O. Dai , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Charles Ryan Wallace
IPC分类号： G06N10/40 , G01R33/035
CPC分类号： G06N10/40 , G01R33/0354
摘要： An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted.

10. 发明授权

US11569976B2 Superconducting isochronous receiver system 有权
公开(公告)号：US11569976B2
公开(公告)日：2023-01-31
申请号：US17340814
申请日：2021-06-07
申请人： Brian Lee Koehler , Corey Arthur Kegerreis , Haitao O. Dai , Quentin P. Herr
发明人： Brian Lee Koehler , Corey Arthur Kegerreis , Haitao O. Dai , Quentin P. Herr
IPC分类号： H04L7/00 , G06F13/40 , G06N10/00 , H03K19/195
摘要： One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.

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