专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07995165B2 LCOS display unit and method for forming the same 有权
标题翻译： LCOS显示单元及其形成方法
公开(公告)号：US07995165B2
公开(公告)日：2011-08-09
申请号：US11851331
申请日：2007-09-06
申请人： Herb He Huang , Xianyong Pu , Jianhong Mao , Yiqun Chen , Jing Fu , Zhongshan Hong , Yanghui Xiang
发明人： Herb He Huang , Xianyong Pu , Jianhong Mao , Yiqun Chen , Jing Fu , Zhongshan Hong , Yanghui Xiang
IPC分类号： G02F1/1335
CPC分类号： G02F1/136277 , G02F1/133553 , G02F1/136209 , H01L27/12 , H01L27/1214 , H01L27/13 , H01L29/78633 , H01L29/78654
摘要： An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.
摘要翻译：本发明的实施例公开了一种液晶硅（LCOS）显示单元，其中通过将光接地而形成由微镜层，绝缘层和遮光层组成的金属 - 绝缘体 - 金属（MIM）电容器像素开关电路层上的屏蔽层。因此，像素开关电路和电容器处于垂直分布，即开关电路和电容器都具有允许的一个像素尺寸的设计区域。本发明的另一个实施例提供了一种用于形成硅晶体（LCOS）显示单元的方法。

2. 发明授权

US08379183B2 LCOS display unit and method for forming the same 有权
标题翻译： LCOS显示单元及其形成方法
公开(公告)号：US08379183B2
公开(公告)日：2013-02-19
申请号：US13155870
申请日：2011-06-08
申请人： Herb He Huang , Xianyong Pu , Jianhong Mao , Yiqun Chen , Jing Fu , Zhongshan Hong , Yanghui Xiang
发明人： Herb He Huang , Xianyong Pu , Jianhong Mao , Yiqun Chen , Jing Fu , Zhongshan Hong , Yanghui Xiang
IPC分类号： G02F1/13 , G02F1/1335
CPC分类号： G02F1/136277 , G02F1/133553 , G02F1/136209 , H01L27/12 , H01L27/1214 , H01L27/13 , H01L29/78633 , H01L29/78654
摘要： An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.
摘要翻译：本发明的实施例公开了一种液晶硅（LCOS）显示单元，其中通过将光接地而形成由微镜层，绝缘层和遮光层组成的金属 - 绝缘体 - 金属（MIM）电容器像素开关电路层上的屏蔽层。因此，像素开关电路和电容器处于垂直分布，即开关电路和电容器都具有允许的一个像素尺寸的设计区域。本发明的另一个实施例提供了一种用于形成硅晶体（LCOS）显示单元的方法。

3. 发明授权

US08058175B2 Method for planarization of wafer and method for formation of isolation structure in top metal layer 有权
标题翻译：晶圆平面化方法及顶层金属层隔离结构形成方法
公开(公告)号：US08058175B2
公开(公告)日：2011-11-15
申请号：US11852918
申请日：2007-09-10
申请人： Herb He Huang , Xianyong Pu , Yi'nan Han , Yiqun Chen
发明人： Herb He Huang , Xianyong Pu , Yi'nan Han , Yiqun Chen
IPC分类号： H01L21/311 , H01B13/00 , C30B33/00 , B44C1/22
CPC分类号： G02F1/133553 , G02F1/136277 , G02F2201/48
摘要： The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.
摘要翻译：本发明公开了一种具有具有凹部的表面层的晶片的平面化方法，包括：在表面层上形成抗蚀剂层以填充整个凹部; 蚀刻抗蚀剂层和表面层，直到凹部外表面层平齐或低于凹部的底部，表面层的蚀刻速度高于抗蚀剂层的蚀刻速度; 去除抗蚀剂层; 并将表面层蚀刻到预定深度。该方法可以避免在现有技术中由化学机械抛光（CMP）工艺产生的晶片表面上的同心环凹槽，并且可以用于获得适合于光学应用的晶片表面。

4. 发明申请

US20120009794A1 Method for Planarization of Wafer and Method for Formation of Isolation Structure in Top Metal Layer 审中-公开
标题翻译：晶圆平面化方法及顶层金属层隔离结构形成方法
公开(公告)号：US20120009794A1
公开(公告)日：2012-01-12
申请号：US13240987
申请日：2011-09-22
申请人： Herb He Huang , Xianyong Pu , Yi'nan Han , Yiqun Chen
发明人： Herb He Huang , Xianyong Pu , Yi'nan Han , Yiqun Chen
IPC分类号： H01L21/311
CPC分类号： G02F1/133553 , G02F1/136277 , G02F2201/48
摘要： The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.
摘要翻译：本发明公开了一种具有具有凹部的表面层的晶片的平面化方法，包括：在表面层上形成抗蚀剂层以填充整个凹部; 蚀刻抗蚀剂层和表面层，直到凹部外表面层平齐或低于凹部的底部，表面层的蚀刻速度高于抗蚀剂层的蚀刻速度; 去除抗蚀剂层; 并将表面层蚀刻到预定深度。该方法可以避免由现有技术中的化学机械抛光（CMP）工艺引起的晶片表面上的同心环凹槽，并且可以用于获得适合于光学应用的晶片表面。

5. 发明申请

US20080081478A1 METHOD FOR PLANARIZATION OF WAFER AND METHOD FOR FORMATION OF ISOLATION STRUCTURE IN TOP METAL LAYER 有权
标题翻译：用于平坦化的方法和在顶部金属层中形成隔离结构的方法
公开(公告)号：US20080081478A1
公开(公告)日：2008-04-03
申请号：US11852918
申请日：2007-09-10
申请人： Herb He Huang , Xianyong Pu , Yi'nan Han , Yiqun Chen
发明人： Herb He Huang , Xianyong Pu , Yi'nan Han , Yiqun Chen
IPC分类号： H01L21/311
CPC分类号： G02F1/133553 , G02F1/136277 , G02F2201/48
摘要： The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.
摘要翻译：本发明公开了一种具有具有凹部的表面层的晶片的平面化方法，包括：在表面层上形成抗蚀剂层以填充整个凹部; 蚀刻抗蚀剂层和表面层，直到凹部外表面层平齐或低于凹部的底部，表面层的蚀刻速度高于抗蚀剂层的蚀刻速度; 去除抗蚀剂层; 并将表面层蚀刻到预定深度。该方法可以避免由现有技术中的化学机械抛光（CMP）工艺引起的晶片表面上的同心环凹槽，并且可以用于获得适合于光学应用的晶片表面。

6. 发明授权

US08422132B2 Integrated planar polarizing device 有权
标题翻译：集成平面偏振装置
公开(公告)号：US08422132B2
公开(公告)日：2013-04-16
申请号：US12629644
申请日：2009-12-02
申请人： Herb He Huang
发明人： Herb He Huang
IPC分类号： G02B5/30
CPC分类号： G02B5/3058 , H04N9/3167
摘要： The embodiments of the present invention provide an integrated planar polarizing device and methods of fabrication. The device, in the order of incidence along an optical path of an incident light beam from back position to front position, comprises a planar array of micro mirrors, a quarter wave retarder film and a reflective polarization plate. The micro mirrors are regularly spaced-apart in an identical tilted angle α relative to a base plane. The quarter wave retarder film is positioned between the micro mirrors and the reflective polarization plate. The reflective polarization plate is in parallel to the base plane and is adapted to transmit and polarize a first polarized light of the incident light beam in a first polarization state, and to reflect and polarize a second polarized light of the incident light beam in a second polarization, The micro mirrors are adapted to reflect the second polarized light passing and polarized through the quarter wave retarder film first time to pass and be polarized through the quarter wave retarder film second time, thereby converting the second polarized light to be a third polarized light in the first polarization state which can transmit the reflective polarization plate. The planar array of micro mirrors, the quarter wave retarder film and the reflective polarization plate are embedded in a transparent medium. The embodiments of the present invention could improve in device integration and simplification in assembly robustness.
摘要翻译：本发明的实施例提供一种集成的平面偏振装置和制造方法。该装置沿着从后方位置到前方位置的入射光束的光路的入射顺序包括微镜的平面阵列，四分之一波长延迟膜和反射偏振板。微反射镜相对于基面以相同的倾斜角α规则地间隔开。四分之一波长延迟膜位于微反射镜和反射偏振板之间。所述反射偏振板与所述基底平面平行，并且适于以第一偏振状态透射和偏振入射光束的第一偏振光，并且在第二偏振态中反射和偏振入射光束的第二偏振光微反射镜适于反射经过四分之一波长延迟器膜的第二偏振光通过第二偏振光并通过四分之一波长延迟片二次偏振，从而将第二偏振光转换为第三偏振光在可以透射反射偏振板的第一偏振状态下。微镜的平面阵列，四分之一波长延迟膜和反射偏振板嵌入透明介质中。本发明的实施例可以在设备集成和组装鲁棒性的简化方面得到改善。

7. 发明授权

US08383489B2 SOI wafer and method for forming the same 有权
标题翻译： SOI晶片及其形成方法
公开(公告)号：US08383489B2
公开(公告)日：2013-02-26
申请号：US12815048
申请日：2010-06-14
申请人： Herb He Huang
发明人： Herb He Huang
IPC分类号： H01L21/76
CPC分类号： H01L21/76254 , H01L21/76283
摘要： An SOI wafer and a method for forming the same, where the method for forming an SOI wafer includes: preparing a monocrystalline silicon wafer on which a mask layer is formed; etching the mask layer and the monocrystalline silicon wafer to form several trenches; forming a first insulating layer on the sidewalls and the bottoms of the trenches; etching and removing the first insulating layer on the bottoms of the trenches; etching along the trenches the monocrystalline silicon wafer beneath the trenches to form cavities; processing the inner walls of the cavities to form a second insulating layer; and filling up the trenches and the cavities with an insulating material layer. The process of the invention is easy to be implemented at a low manufacturing cost and an SOI wafer being formed is of high quality while being capable of being compatible with a standard process of manufacturing a bulk silicon CMOS.
摘要翻译： SOI晶片及其形成方法，其中SOI晶片的形成方法包括：制备其上形成有掩模层的单晶硅晶片; 蚀刻掩模层和单晶硅晶片以形成若干沟槽; 在沟槽的侧壁和底部上形成第一绝缘层; 蚀刻并去除沟槽底部的第一绝缘层; 沿着沟槽蚀刻沟槽下面的单晶硅晶片以形成空腔; 处理空腔的内壁以形成第二绝缘层; 并用绝缘材料层填充沟槽和空腔。本发明的方法易于以低制造成本实现，并且形成的SOI晶片具有高质量，同时能够与制造体硅CMOS的标准工艺兼容。

8. 发明授权

US08043891B2 Method of encapsulating a wafer level microdevice 有权
标题翻译：封装晶圆级微器件的方法
公开(公告)号：US08043891B2
公开(公告)日：2011-10-25
申请号：US12793295
申请日：2010-06-03
申请人： Herb He Huang
发明人： Herb He Huang
IPC分类号： H01L21/00 , H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： B81C1/00333 , B81C2203/0118
摘要： The present invention discloses a method of encapsulating a wafer level microdevice, which includes: fabricating a microdevice on top side of a first silicon wafer; depositing a first capping carbon film on the top side of the first silicon wafer; implementing a backside fabricating process of wafer from bottom side of the first silicon wafer by carrying the top side of the first silicon wafer through the first capping carbon film; removing the first capping carbon film by selective gaseous reaction with carbon; and encapsulating an encapsulation wafer onto the top side of the first silicon wafer. The present invention deposits and removes the first capping carbon film by means of chemical technology, thereby protecting the microdevice on the top side of the first wafer during implementing the backside fabricating process of wafer. The top side does not need to be protected through the encapsulation wafer before implementing the backside fabricating process of wafer, which makes the wafer thinner and convenient to be handled.
摘要翻译：本发明公开了一种封装晶片级微器件的方法，其包括：在第一硅晶片的顶侧上制造微型器件; 在第一硅晶片的顶侧上沉积第一封盖碳膜; 通过将第一硅晶片的顶侧通过第一封盖碳膜，从第一硅晶片的底侧实现晶片的背面制造工艺; 通过与碳的选择性气相反应去除第一封盖碳膜; 并将封装晶片封装在第一硅晶片的顶侧上。本发明通过化学技术沉积和去除第一封盖碳膜，从而在实现晶片的背面制造工艺期间保护微型器件在第一晶片的顶侧上。在实施晶片的背面制造工艺之前，顶侧不需要通过封装晶片进行保护，这使得晶片更薄且便于处理。

9. 发明授权

US08854720B2 Tri wavelength diffraction modulator and a method for modulation 有权
$Tri wavelength diffraction modulator and a method for modulation$
标题翻译：三波长衍射调制器和调制方法
公开(公告)号：US08854720B2
公开(公告)日：2014-10-07
申请号：US13540356
申请日：2012-07-02
申请人： Herb He Huang
发明人： Herb He Huang
IPC分类号： G02B26/00 , G02B27/42 , G02B5/18 , G09G5/00 , G02B26/08 , G02F1/21
CPC分类号： G02B26/0808 , G02F1/21
摘要： The present invention relates to a tri wavelength diffraction modulator (TWDM) and a method of tri wavelength diffraction modulation. The tri wavelength diffraction modulator includes: a stationary substrate with a bottom electrode plate formed on top of the stationary substrate; a first electrode plate comprising a first suspended beam suspended in parallel above the stationary substrate and a first connection anchored onto the stationary substrate; and a second electrode plate comprising a second suspended beam suspended in parallel above the first electrode plate and a second connection anchored onto the stationary substrate. The diffraction modulator and the method for diffraction modulation are suitable to projection system.
摘要翻译：本发明涉及三波长衍射调制器（TWDM）和三波长衍射调制方法。三波长衍射调制器包括：固定基板，其具有形成在固定基板的顶部上的底部电极板; 第一电极板，包括平行地悬挂在固定基板上的第一悬挂梁和锚固在固定基板上的第一连接件; 以及第二电极板，包括平行地悬挂在第一电极板上方的第二悬挂梁和锚固在固定基板上的第二连接件。衍射调制器和衍射调制方法适用于投影系统。

10. 发明授权

US08467128B2 Polarizing cube and method of fabricating the same 有权
标题翻译：极化立方体及其制造方法
公开(公告)号：US08467128B2
公开(公告)日：2013-06-18
申请号：US12622382
申请日：2009-11-19
申请人： Herb He Huang
发明人： Herb He Huang
IPC分类号： G02B5/30
CPC分类号： G02B5/3058 , G02B27/283
摘要： A polarizing cube includes a pair of identical and symmetric triangular prisms which sandwich a thin optical composite plate containing a planner array of reflective straight wires spaced apart in parallel as a built-in wire grid polarizer. All of its subcomponents and the polarizing cube itself are physically and optically symmetrical to one of its diagonal planes so as to provide improved integration and robustness for projection display application. The cubic configuration of the disclosed polarizer can be readily produced through common means and sequences typically used in semiconductor wafer fabrication processes, including photolithographic patterning, gap dielectric filling and planarization, and wafer thinning, bonding and cutting among others.
摘要翻译：偏振立方体包括一对相同和对称的三角形棱镜，其夹持包含平行间隔开的反射直线的计划器阵列作为内置线栅偏振器的薄光学复合板。其所有子部件和偏振立方体本身都与其对角平面之一物理和光学对称，从而为投影显示应用提供改进的集成度和鲁棒性。所公开的偏振器的立方体结构可以通过通常用于半导体晶片制造工艺中的常用手段和序列容易地产生，包括光刻图案，间隙介电填充和平面化，以及晶片间隔，结合和切割等。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式