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1. 发明授权

US5122676A Variable pulse width generator including a timer vernier 失效
标题翻译：可变脉冲宽度发生器，包括定时器VERNIER
公开(公告)号：US5122676A
公开(公告)日：1992-06-16
申请号：US620681
申请日：1990-12-03
申请人： Roger G. Stewart , George R. Briggs
发明人： Roger G. Stewart , George R. Briggs
IPC分类号： G09G3/20 , G09G3/36 , H03M1/82
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0259 , G09G2310/027
摘要： A pulse logic circuit comprises a plurality of interconnected stages. Each of the stages includes a relatively large node-charging transistor which, when enabled, forwards charging current to a node from a timing pulse of one of a plurality of phases applied to a load capacitance in series with the node-charging transistor. Such large transistors exhibit significant gate-to-source and gate-to drain distributed capacitances. The response time for charging a selected stage node can be decreased by precharging the gate of the node-charging transistor of a selected stage to enable the transistor prior to the application of a timing pulse, thereby increasing the maximum operating speed of the circuit. Disclosed species of such a pulse logic circuit include time vernier circuits which can be utilized as control circuitry for a liquid crystal television or computer display.
摘要翻译：脉冲逻辑电路包括多个互连级。每个级包括相对较大的节点充电晶体管，其在使能时，从施加到与节点充电晶体管串联的负载电容的多个相中的一个相的定时脉冲向节点转发充电电流。这种大型晶体管表现出显着的栅极到源极和栅极到漏极分布电容。通过对选定级的节点充电晶体管的栅极进行预充电，可以在施加定时脉冲之前使晶体管使能，从而提高电路的最大工作速度，可以减小对选定级节点充电的响应时间。这种脉冲逻辑电路的公开物种包括可用作液晶电视或计算机显示器的控制电路的时间游标电路。

2. 发明授权

US5093581A Circuitry for generating pulses of variable widths from binary input data 失效
标题翻译：用于从二进制输入数据产生可变宽度的脉冲的电路
公开(公告)号：US5093581A
公开(公告)日：1992-03-03
申请号：US620684
申请日：1990-12-03
申请人： George R. Briggs , Roger G. Stewart
发明人： George R. Briggs , Roger G. Stewart
IPC分类号： G09G3/36 , G09G3/20 , H03K5/00 , H03K5/13 , H03K5/135 , H03K7/08 , H03M1/82
CPC分类号： H03K7/08 , H03K5/131 , H03K5/135 , H03K2005/00195
摘要： A variable width pulse generator includes a plurality of logic stages which are coupled in cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the variable width pulse.
摘要翻译：可变宽度脉冲发生器包括级联耦合的多个逻辑级。每个级被布置成响应于定义脉冲宽度的数据字的特定位来选择施加到其上的不同相位的多个时钟信号中的一个。所有阶段最初由在每个可变脉冲间隔开始时发生的预充电脉冲而被禁用。通过出现由前一级选择的时钟信号的时钟脉冲使连续级能够实现。最后一个阶段提供对应于可变宽度脉冲的输出。

3. 发明授权

US08936201B2 Integrated circuits with persistent data storage 有权
标题翻译：具有持久数据存储的集成电路
公开(公告)号：US08936201B2
公开(公告)日：2015-01-20
申请号：US13900296
申请日：2013-05-22
申请人： Curtis L. Carrender , Roger G. Stewart , John H. Rolin , Ronald Gilbert
发明人： Curtis L. Carrender , Roger G. Stewart , John H. Rolin , Ronald Gilbert
IPC分类号： G06K19/06 , G06K7/10 , G06K19/07 , G06K19/073
CPC分类号： G06K19/0723 , G06K7/10019 , G06K19/07381
摘要： The circuitry introduced in this invention selectively slows down the functioning of an electronic circuit maintaining a particular state for a prolonged period of time. This circuitry is used not only to achieve the desired effect in maintaining security from electronic thieves trying to circumvent codes but also in other applications such as enabling a circuit to continue to function in the event of a brief loss of power. For example, in an RFID system, if a reader is frequency hopping, a tag loses power for as long as about 400 milliseconds when the reader changes to other frequencies. In a preferred embodiment, the disclosed circuitry is used in conjunction with a destruct sequence.
摘要翻译：在本发明中引入的电路选择性地减慢保持特定状态长时间的电子电路的功能。该电路不仅用于在维护电子窃贼试图绕过代码的安全性方面实现期望的效果，而且在其他应用中，例如使电路在短暂的功率损失的情况下继续工作。例如，在RFID系统中，如果读取器跳频，当读取器改变到其他频率时，标签失去长达约400毫秒的功率。在优选实施例中，所公开的电路与破坏序列结合使用。

4. 发明授权

US08464957B2 Integrated circuits with persistent data storage 有权
标题翻译：具有持久数据存储的集成电路
公开(公告)号：US08464957B2
公开(公告)日：2013-06-18
申请号：US13276222
申请日：2011-10-18
申请人： Curtis L. Carrender , Roger G. Stewart , John H. Rolin , Ronald Gilbert
发明人： Curtis L. Carrender , Roger G. Stewart , John H. Rolin , Ronald Gilbert
IPC分类号： G06K19/06
CPC分类号： G06K19/0723 , G06K7/10019 , G06K19/07381
摘要： A tag receives a first code transmitted by an RFID reader. The first code is compared with a second code stored within the tag. If the first code and the second code match, the tag transmits a third code to the RFID reader.
摘要翻译：标签接收由RFID读取器发送的第一代码。第一个代码与存储在标签中的第二个代码进行比较。如果第一代码和第二代码匹配，则标签将第三代码发送到RFID读取器。

5. 发明授权

US5587329A Method for fabricating a switching transistor having a capacitive network proximate a drift region 失效
标题翻译：一种用于制造具有靠近漂移区域的电容网络的开关晶体管的方法
公开(公告)号：US5587329A
公开(公告)日：1996-12-24
申请号：US295374
申请日：1994-08-24
申请人： Fu-Lung Hseuh , Alfred C. Ipri , Gary M. Dolny , Roger G. Stewart
发明人： Fu-Lung Hseuh , Alfred C. Ipri , Gary M. Dolny , Roger G. Stewart
IPC分类号： H01L29/786 , G09G3/30 , H01L27/088 , H01L27/12 , H01L21/786
CPC分类号： H01L27/1203 , G09G3/30 , H01L27/088 , H01L27/12 , G09G2300/0842
摘要： In an active matrix electroluminescent display, a pixel containing a grounded conductive electric field shield between an EL cell and the switching electronics for the EL cell. In a method of fabricating the pixel, first, an EL cell switching circuit is formed, then an insulating layer is formed over the switching circuit and a conductive layer (the field shield) is formed over the insulating layer. A through hole is provided in the field shield such that an electrical connection can be made between the switching circuit and an EL cell. The EL cell is then conventionally formed on top of the shield layer. Consequently, the shield isolates the switching circuit from the EL cell and ensures that any electric fields produced in the EL cell do not interfere with the operation of the switching electronics. Furthermore, the switching circuitry for each cell contains two transistors; a low voltage MOS transistor and a high voltage MOS transistor. The low voltage transistor is controlled by signals on a data and a select line. When activated, the low voltage transistor activates the high voltage transistor by charging the gate of the high voltage transistor. This gate charge is stored between the gate electrode of the high voltage transistor and the electric field shield. Additionally, to improve the breakdown voltage of the high voltage transistor, a capacitive divider network is fabricated proximate the drift region of that transistor. As such, the network uniformly distributes an electric field over the drift region.
摘要翻译：在有源矩阵电致发光显示器中，包含EL单元和用于EL单元的开关电子器件之间的接地导电电场屏蔽的像素。在制造像素的方法中，首先，形成EL单元切换电路，然后在开关电路上形成绝缘层，并且在绝缘层上形成导电层（场屏蔽）。在屏蔽层中设置通孔，使得可以在开关电路和EL单元之间形成电连接。然后通常将EL电池形成在屏蔽层的顶部。因此，屏蔽将开关电路与EL单元隔离，并确保在EL单元中产生的任何电场不会干扰开关电子器件的操作。此外，每个单元的开关电路包含两个晶体管; 低压MOS晶体管和高压MOS晶体管。低电压晶体管由数据和选择线上的信号控制。当激活时，低压晶体管通过对高电压晶体管的栅极充电来激活高电压晶体管。该栅极电荷存储在高电压晶体管的栅电极和电场屏蔽之间。另外，为了提高高压晶体管的击穿电压，在该晶体管的漂移区附近制造电容分压网络。这样，网络在漂移区域上均匀地分布电场。

6. 发明授权

US5122792A Electronic time vernier circuit 失效
标题翻译：电子时间维修电路
公开(公告)号：US5122792A
公开(公告)日：1992-06-16
申请号：US541653
申请日：1990-06-21
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G09G3/00 , G09G3/20 , G09G3/36 , H03K5/13 , H03K7/08 , H04N1/405
CPC分类号： G09G3/2011 , G09G3/3688 , H03K5/133 , H03K7/08 , H04N1/4056 , G09G2310/0259 , G09G2310/027
摘要： A drive circuit for a liquid crystal display converts a display information signal to an n bit gray scale code to control the brightness at a prescribed pixel. A counter receives the m most significant bits of the n bit gray scale code and a latch receives the n-m least significant bits of the n bit gray scale code. The counter is decremented by clock pulses occurring at predetermined intervals and a set of 2.sup.n-m sub-interval timing signals are generated in response to each clock pulse. A transfer gate is enabled by an interval initiating pulse to permit charging of the pixel. One of the sub-interval timing signals is selected in response to the n-m least significant bits of the n bit gray scale code stored in the latch. The transfer gate is disabled by the sub-interval timing signal immediately succeeding the decrementing of the counter to its zero state.
摘要翻译：用于液晶显示器的驱动电路将显示信息信号转换为n位灰度代码，以控制规定像素处的亮度。计数器接收n位灰度代码的m个最高有效位，并且锁存器接收n位灰度代码的n-m个最低有效位。计数器由以预定间隔发生的时钟脉冲递减，并且响应于每个时钟脉冲产生一组2n-m个次间隔定时信号。传输门通过间隔起始脉冲启用以允许对像素充电。响应于存储在锁存器中的n位灰度代码的n-m个最低有效位来选择子间隔定时信号之一。传输门由紧邻计数器递减到其零状态的子间隔定时信号禁用。

7. 发明授权

US4965646A Thin film transistor and crossover structure for liquid crystal displays 失效
标题翻译：薄膜晶体管和液晶显示器的交叉结构
公开(公告)号：US4965646A
公开(公告)日：1990-10-23
申请号：US260845
申请日：1988-10-21
申请人： Alfred C. Ipri , Roger G. Stewart
发明人： Alfred C. Ipri , Roger G. Stewart
IPC分类号： G02F1/136 , G02F1/1368 , G09F9/30 , H01L21/768 , H01L23/522 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： G02F1/13454 , G02F1/1368 , G02F2001/136231
摘要： A three-mask process for fabricating liquid crystal devices enables the simultaneous fabrication of thin film transistors and conductor crossovers, thereby permitting the simultaneous fabrication of drive circuitry on the periphery of the devices.

8. 发明授权

US4963860A Integrated matrix display circuitry 失效
标题翻译：集成矩阵显示电路
公开(公告)号：US4963860A
公开(公告)日：1990-10-16
申请号：US150812
申请日：1988-02-01
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/3677 , G09G3/3648 , G09G3/3688 , G09G2310/0205 , G09G2310/0224 , G09G2310/0297
摘要： A matrix display apparatus fabricated in low mobility material includes integrated commutating circuitry for applying data signals to the display elements. The commutating circuitry includes demultiplexing circuitry coupled to a first set of latch elements. These latch elements are coupled to a second set of latch elements via transmission gates, and the output terminals of the second set of latch elements are coupled to column buffers. The demultiplexing circuitry includes pass transistors to coupled display signals to respective ones of the first set of latches. The first set of latches are preconditioned by appropriate timing signals so that the demultiplexor pass transistors operate in a common source mode to shorten the overall switching time of the commutating circuitry.
摘要翻译：以低迁移率材料制造的矩阵显示装置包括用于向显示元件施加数据信号的集成整流电路。整流电路包括耦合到第一组锁存元件的解复用电路。这些锁存元件经由传输门耦合到第二组锁存元件，并且第二组锁存元件的输出端耦合到列缓冲器。解复用电路包括传输晶体管以将显示信号耦合到第一组锁存器中的相应的一个。第一组锁存器由适当的定时信号预处理，使得解复用器传递晶体管以共同的源模式工作，以缩短整流电路的整体切换时间。

9. 发明授权

US4766430A Display device drive circuit 失效
标题翻译：显示设备驱动电路
公开(公告)号：US4766430A
公开(公告)日：1988-08-23
申请号：US943496
申请日：1986-12-19
申请人： Glynn G. Gillette , Roger G. Stewart , John T. Fischer
发明人： Glynn G. Gillette , Roger G. Stewart , John T. Fischer
IPC分类号： G09G3/20 , G09G3/36 , H04N3/12
CPC分类号： G09G3/2011 , G09G3/3688 , H04N3/127 , G09G2310/0259 , G09G2310/027
摘要： A drive circuit for a liquid crystal display includes a counter for each column of the display. The counters are set with brightness counts to establish the grey scales for the pixels. The counters turn transfer gates on when a count is present and off when the count is zero. An analog generator biases the columns through the transfer gates so that each column is biased to a level determined by the brightness count of the respective counter.
摘要翻译：用于液晶显示器的驱动电路包括用于显示器的每列的计数器。计数器设置有亮度计数，以建立像素的灰度级。当计数存在时，计数器打开传输门，当计数为零时，计数器关闭。模拟发生器通过传输门偏置列，使得每列被偏置到由相应计数器的亮度计数确定的电平。

10. 发明授权

US4618876A Electrically alterable, nonvolatile floating gate memory device 失效
标题翻译：电动可变的非易失性浮栅存储器件
公开(公告)号：US4618876A
公开(公告)日：1986-10-21
申请号：US633188
申请日：1984-07-23
申请人： Roger G. Stewart , Alfred C. Ipri
发明人： Roger G. Stewart , Alfred C. Ipri
IPC分类号： H01L29/788 , H01L29/34
CPC分类号： H01L29/7883
摘要： A floating gate structure wherein the floating gate is a second level polysilicon layer that is substantially shielded from the substrate by a segmented, discontinuous first level word line. Coupling of the floating gate to the substrate for "writing" is accomplished by extending the floating gate between word line segments while electrical continuity of the word line is maintained by buried contacts which make electrical contact to a continuous third level polysilicon layer.
摘要翻译：一种浮动栅极结构，其中浮置栅极是通过分段的不连续的第一级字线基本上与衬底屏蔽的第二级多晶硅层。通过在字线段之间延伸浮动栅极，同时通过与连续的第三级多晶硅层进行电接触的埋入触点来维持字线的连续性来实现浮置栅极与基板的“写入”耦合。

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